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[Hexagon] Support lowering of setuo & seto for vector types in Hexagon #158740

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Merged
merged 6 commits into from
Oct 3, 2025
Merged

[Hexagon] Support lowering of setuo & seto for vector types in Hexagon #158740

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6588982
[Hexagon] Support lowering of setuo & seto for vector types in Hexagon
kaushik-quicinc May 22, 2025
deeed94
Add check for setO
fhossein-quic Sep 16, 2025
6cd424a
add checks for second var as an operand
fhossein-quic Oct 2, 2025
5957719
clang-format
fhossein-quic Oct 2, 2025
381fb2f
Merge branch 'main' into upstream_setuo_seto
fhossein-quic Oct 3, 2025
1298609
Merge branch 'main' into upstream_setuo_seto
fhossein-quic Oct 3, 2025
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4 changes: 4 additions & 0 deletions llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -355,6 +355,8 @@ HexagonTargetLowering::initializeHVXLowering() {
setCondCodeAction(ISD::SETULE, MVT::v64f16, Expand);
setCondCodeAction(ISD::SETUGE, MVT::v64f16, Expand);
setCondCodeAction(ISD::SETULT, MVT::v64f16, Expand);
setCondCodeAction(ISD::SETUO, MVT::v64f16, Expand);
setCondCodeAction(ISD::SETO, MVT::v64f16, Expand);

setCondCodeAction(ISD::SETNE, MVT::v32f32, Expand);
setCondCodeAction(ISD::SETLE, MVT::v32f32, Expand);
Expand All @@ -368,6 +370,8 @@ HexagonTargetLowering::initializeHVXLowering() {
setCondCodeAction(ISD::SETULE, MVT::v32f32, Expand);
setCondCodeAction(ISD::SETUGE, MVT::v32f32, Expand);
setCondCodeAction(ISD::SETULT, MVT::v32f32, Expand);
setCondCodeAction(ISD::SETUO, MVT::v32f32, Expand);
setCondCodeAction(ISD::SETO, MVT::v32f32, Expand);

// Boolean vectors.

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74 changes: 74 additions & 0 deletions llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll
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@@ -0,0 +1,74 @@
;; RUN: llc --mtriple=hexagon -mattr=+hvxv79,+hvx-length128b %s -o - | FileCheck %s

define dso_local void @store_isnan_f32(ptr %a, ptr %isnan_a) local_unnamed_addr {
entry:
%arrayidx = getelementptr inbounds nuw float, ptr %a, i32 0
%0 = load <32 x float>, ptr %arrayidx, align 4
%.vectorized = fcmp uno <32 x float> %0, zeroinitializer
%.LS.instance = zext <32 x i1> %.vectorized to <32 x i32>
%arrayidx1 = getelementptr inbounds nuw i32, ptr %isnan_a, i32 0
store <32 x i32> %.LS.instance, ptr %arrayidx1, align 4
ret void
}
; CHECK: store_isnan_f32
; CHECK: [[VZERO32:v[0-9]+]] = vxor([[VZERO32]],[[VZERO32]])
; CHECK: [[VLOAD32:v[0-9]+]] = vmemu(r0+#0)
; CHECK: [[VONES32:v[0-9]+]] = vsplat([[RONE32:r[0-9]+]])
; CHECK: {{q[0-9]+}} = vcmp.eq([[VLOAD32]].w,[[VLOAD32]].w)
; CHECK: [[VOUT32:v[0-9]+]] = vmux({{q[0-9]+}},[[VZERO32]],[[VONES32]])
; CHECK: vmemu(r1+#0) = [[VOUT32]]


define dso_local void @store_isnan_f16(ptr %a, ptr %isnan_a) local_unnamed_addr {
entry:
%arrayidx = getelementptr inbounds nuw half, ptr %a, i32 0
%0 = load <64 x half>, ptr %arrayidx, align 2
%.vectorized = fcmp uno <64 x half> %0, zeroinitializer
%conv.LS.instance = zext <64 x i1> %.vectorized to <64 x i16>
%arrayidx1 = getelementptr inbounds nuw i16, ptr %isnan_a, i32 0
store <64 x i16> %conv.LS.instance, ptr %arrayidx1, align 2
ret void
}
; CHECK: store_isnan_f16
; CHECK: [[VZERO16:v[0-9]+]] = vxor([[VZERO16]],[[VZERO16]])
; CHECK: [[VLOAD16:v[0-9]+]] = vmemu(r0+#0)
; CHECK: [[VONES16:v[0-9]+]].h = vsplat([[RONE16:r[0-9]+]])
; CHECK: {{q[0-9]+}} = vcmp.eq([[VLOAD16]].h,[[VLOAD16]].h)
; CHECK: [[VOUT16:v[0-9]+]] = vmux({{q[0-9]+}},[[VZERO16]],[[VONES16]])
; CHECK: vmemu(r1+#0) = [[VOUT16]]

define dso_local void @store_isordered_f32(ptr %a, ptr %isordered_a) local_unnamed_addr {
entry:
%arrayidx = getelementptr inbounds nuw float, ptr %a, i32 0
%0 = load <32 x float>, ptr %arrayidx, align 4
%.vectorized = fcmp ord <32 x float> %0, zeroinitializer
%.LS.instance = zext <32 x i1> %.vectorized to <32 x i32>
%arrayidx1 = getelementptr inbounds nuw i32, ptr %isordered_a, i32 0
store <32 x i32> %.LS.instance, ptr %arrayidx1, align 4
ret void
}
; CHECK: store_isordered_f32
; CHECK: [[V_ZERO32:v[0-9]+]] = vxor([[V_ZERO32]],[[V_ZERO32]])
; CHECK: [[V_LOAD32:v[0-9]+]] = vmemu(r0+#0)
; CHECK: [[V_ONES32:v[0-9]+]] = vsplat([[RO32:r[0-9]+]])
; CHECK: {{q[0-9]+}} = vcmp.eq([[V_LOAD32]].w,[[V_LOAD32]].w)
; CHECK: [[V_OUT32:v[0-9]+]] = vmux({{q[0-9]+}},[[V_ONES32]],[[V_ZERO32]])
; CHECK: vmemu(r1+#0) = [[V_OUT32]]

define dso_local void @store_isordered_f16(ptr %a, ptr %isordered_a) local_unnamed_addr {
entry:
%arrayidx = getelementptr inbounds nuw half, ptr %a, i32 0
%0 = load <64 x half>, ptr %arrayidx, align 2
%.vectorized = fcmp ord <64 x half> %0, zeroinitializer
%conv.LS.instance = zext <64 x i1> %.vectorized to <64 x i16>
%arrayidx1 = getelementptr inbounds nuw i16, ptr %isordered_a, i32 0
store <64 x i16> %conv.LS.instance, ptr %arrayidx1, align 2
ret void
}
; CHECK: store_isordered_f16
; CHECK: [[V_ZERO16:v[0-9]+]] = vxor([[V_ZERO16]],[[V_ZERO16]])
; CHECK: [[V_LOAD16:v[0-9]+]] = vmemu(r0+#0)
; CHECK: [[V_ONES16:v[0-9]+]].h = vsplat([[RO16:r[0-9]+]])
; CHECK: {{q[0-9]+}} = vcmp.eq([[V_LOAD16]].h,[[V_LOAD16]].h)
; CHECK: [[V_OUT16:v[0-9]+]] = vmux({{q[0-9]+}},[[V_ONES16]],[[V_ZERO16]])
; CHECK: vmemu(r1+#0) = [[V_OUT16]]
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Thanks for adding more test cases, but none of these examples here are great because the second operand is 0. Can you add testcases where the second operand to fcmp is not 0?

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Thanks for catching this. I've made changes so that the second operand is a var as well. Please let me know if it addresses your comment