RISCV: the builtins support for MIPS RV64 P8700 execution control .

clang/include/clang/Basic/BuiltinsRISCV.td

@@ -162,3 +162,8 @@ include "clang/Basic/BuiltinsRISCVXCV.td"
 // XAndes extensions.
 //===----------------------------------------------------------------------===//
 include "clang/Basic/BuiltinsRISCVXAndes.td"
+
+//===----------------------------------------------------------------------===//
+// MIPS extensions.
+//===----------------------------------------------------------------------===//
+include "clang/Basic/BuiltinsRISCVXMIPS.td"

clang/include/clang/Basic/BuiltinsRISCVXMIPS.td

@@ -0,0 +1,21 @@
+//==- BuiltinsRISCVXMIPS.td - RISC-V MIPS  Builtin database    ----*- C++ -*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the MIPS-specific builtin function database.  Users of
+// this file must define the BUILTIN macro to make use of this information.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// MIPS execution control extensions.
+//===----------------------------------------------------------------------===//
+let Attributes = [NoThrow, Const] in {
+def mips_pause : RISCVBuiltin<"void()", "xmipsexectl">;
+def mips_ehb   : RISCVBuiltin<"void()", "xmipsexectl">;
+def mips_ihb   : RISCVBuiltin<"void()", "xmipsexectl">;
+}

clang/test/CodeGen/builtins-riscv-mips.c

@@ -0,0 +1,35 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6
+// RUN: %clang_cc1 -triple riscv32-linux-elf -O3  -target-feature +xmipsexectl -emit-llvm -o - %s  | FileCheck %s
+
+// CHECK-LABEL: define dso_local void @test_mips_pause(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    tail call void @llvm.riscv.mips.pause()
+// CHECK-NEXT:    ret void
+//
+void test_mips_pause()
+{
+	__builtin_riscv_mips_pause();
+}
+
+// CHECK-LABEL: define dso_local void @test_mips_ehb(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    tail call void @llvm.riscv.mips.ehb()
+// CHECK-NEXT:    ret void
+//
+void test_mips_ehb()
+{
+	__builtin_riscv_mips_ehb();
+}
+
+// CHECK-LABEL: define dso_local void @test_mips_ihb(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    tail call void @llvm.riscv.mips.ihb()
+// CHECK-NEXT:    ret void
+//
+void test_mips_ihb()
+{
+	__builtin_riscv_mips_ihb();
+}

llvm/include/llvm/IR/IntrinsicsRISCV.td

@@ -1949,3 +1949,4 @@ include "llvm/IR/IntrinsicsRISCVXTHead.td"
 include "llvm/IR/IntrinsicsRISCVXsf.td"
 include "llvm/IR/IntrinsicsRISCVXCV.td"
 include "llvm/IR/IntrinsicsRISCVXAndes.td"
+include "llvm/IR/IntrinsicsRISCVXMIPS.td"

llvm/include/llvm/IR/IntrinsicsRISCVXMIPS.td

@@ -0,0 +1,20 @@
+//===- IntrinsicsRISCVXMIPS.td - MIPS intrinsics -------*- tablegen -*----===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines all of the MIPS specific intrinsics for RISC-V.
+//
+//===----------------------------------------------------------------------===//
+
+let TargetPrefix = "riscv" in {
+  def int_riscv_mips_pause : ClangBuiltin<"__builtin_riscv_mips_pause">,
+        Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>;
+  def int_riscv_mips_ehb : ClangBuiltin<"__builtin_riscv_mips_ehb">,
+        Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>;
+  def int_riscv_mips_ihb : ClangBuiltin<"__builtin_riscv_mips_ihb">,
+        Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>;
+}

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -1426,7 +1426,7 @@ def NoVendorXMIPSCBOP : Predicate<"!Subtarget->hasVendorXMIPSCBOP()">;
 
 def FeatureVendorXMIPSEXECTL : RISCVExtension<1, 0, "MIPS execution control">;
 def HasVendorXMIPSEXECTL
-    : Predicate<"Subtarget->hasVendorXMIPSEXT()">,
+    : Predicate<"Subtarget->hasVendorXMIPSEXECTL()">,
       AssemblerPredicate<(all_of FeatureVendorXMIPSEXECTL),
                          "'Xmipsexectl' (MIPS execution control)">;
 

llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td

@@ -143,6 +143,13 @@ let Predicates = [HasVendorXMIPSEXECTL], DecoderNamespace = "XMIPS" in {
   def MIPS_PAUSE : MIPSExtInst_ri<0b000101, "mips.pause">;
 }
 
+let Predicates = [HasVendorXMIPSEXECTL] in {
+  // Intrinsics
+  def : Pat<(int_riscv_mips_pause), (MIPS_PAUSE)>;
+  def : Pat<(int_riscv_mips_ihb), (MIPS_IHB)>;
+  def : Pat<(int_riscv_mips_ehb), (MIPS_EHB)>;
+}
+
 let Predicates = [HasVendorXMIPSCBOP], DecoderNamespace = "XMIPS" in {
   def MIPS_PREF : Mips_prefetch_ri<(outs), (ins GPR:$rs1, uimm9:$imm9, uimm5:$hint),
                                     "mips.pref", "$hint, ${imm9}(${rs1})">,

llvm/test/CodeGen/RISCV/xmips-exectl.ll

@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=riscv64 -mcpu=mips-p8700 -O3  -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=MIPS %s
+
+target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
+
+define void @test_mips_pause() {
+; MIPS-LABEL: test_mips_pause:
+; MIPS:       # %bb.0: # %entry
+; MIPS-NEXT:    mips.pause
+; MIPS-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.mips.pause()
+  ret void
+}
+
+define void @test_mips_ehb() {
+; MIPS-LABEL: test_mips_ehb:
+; MIPS:       # %bb.0: # %entry
+; MIPS-NEXT:    mips.ehb
+; MIPS-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.mips.ehb()
+  ret void
+}
+
+define void @test_mips_ihb() {
+; MIPS-LABEL: test_mips_ihb:
+; MIPS:       # %bb.0: # %entry
+; MIPS-NEXT:    mips.ihb
+; MIPS-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.mips.ihb()
+  ret void
+}