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[ROCDL][LLVM] Added rocdl.fmed3 -> Intrinsic::amdgcn_fmed3 #159332

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Merged
merged 5 commits into from
Sep 29, 2025
Merged

[ROCDL][LLVM] Added rocdl.fmed3 -> Intrinsic::amdgcn_fmed3 #159332

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285f502
Added fmed3 rocdl op
keshavvinayak01 Sep 17, 2025
776fc40
Merge branch 'main' into users/keshavvinayak01/clampf-fmed-rocdl
keshavvinayak01 Sep 17, 2025
829dc0f
Variadic rocdl.fmed3 op; print tests; addresed comments
keshavvinayak01 Sep 21, 2025
15528e6
Merge branch 'main' into users/keshavvinayak01/clampf-fmed-rocdl
keshavvinayak01 Sep 27, 2025
875580f
Merge branch 'main' into users/keshavvinayak01/clampf-fmed-rocdl
keshavvinayak01 Sep 28, 2025
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20 changes: 20 additions & 0 deletions mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1291,6 +1291,26 @@ def ROCDL_CvtScaleF32PkFp4F32Op :
}];
}

//===----------------------------------------------------------------------===//
// MED3 operations
//===----------------------------------------------------------------------===//

def ROCDL_Med3Op : ROCDL_ConcreteNonMemIntrOp<"med3", [Pure, AllTypesMatch<["res", "src0", "src1", "src2"]>], 1>,
Arguments<(ins LLVM_ScalarOrVectorOf<LLVM_AnyFloat>:$src0,
LLVM_ScalarOrVectorOf<LLVM_AnyFloat>:$src1,
LLVM_ScalarOrVectorOf<LLVM_AnyFloat>:$src2)> {
let results = (outs LLVM_ScalarOrVectorOf<LLVM_AnyFloat>:$res);
let summary = "Median of three float/half values";
let assemblyFormat = [{
$src0 `,` $src1 `,` $src2 attr-dict `:` `(` type($src0) `,` type($src1) `,` type($src2) `)` `->` type($res)
}];
string llvmBuilder = [{
$res = createIntrinsicCall(builder, llvm::Intrinsic::amdgcn_fmed3,
{$src0, $src1, $src2},
{moduleTranslation.convertType(op.getRes().getType())});
}];
}

//===----------------------------------------------------------------------===//
// ROCDL target attribute.
//===----------------------------------------------------------------------===//
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14 changes: 14 additions & 0 deletions mlir/test/Target/LLVMIR/rocdl.mlir
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Expand Up @@ -1298,6 +1298,20 @@ llvm.func @rocdl_last_use(%ptr: !llvm.ptr<1>) -> i32 {
llvm.return %ret : i32
}

llvm.func @test_med3_f16(%arg0: f16, %arg1: f16, %arg2: f16) -> f16 {
// CHECK-LABEL: define half @test_med3_f16(half %0, half %1, half %2)
%0 = rocdl.med3 %arg0, %arg1, %arg2 : (f16, f16, f16) -> f16
llvm.return %0 : f16
// CHECK: call half @llvm.amdgcn.fmed3.f16(half %0, half %1, half %2)
}

llvm.func @test_med3_f32(%arg0: f32, %arg1: f32, %arg2: f32) -> f32 {
// CHECK-LABEL: define float @test_med3_f32(float %0, float %1, float %2)
%0 = rocdl.med3 %arg0, %arg1, %arg2 : (f32, f32, f32) -> f32
llvm.return %0 : f32
// CHECK: call float @llvm.amdgcn.fmed3.f32(float %0, float %1, float %2)
}

// CHECK-DAG: attributes #[[$KERNEL_ATTRS]] = { "amdgpu-flat-work-group-size"="1,256" "uniform-work-group-size"="true" }
// CHECK-DAG: attributes #[[$KERNEL_WORKGROUP_ATTRS]] = { "amdgpu-flat-work-group-size"="1,1024"
// CHECK-DAG: attributes #[[$KNOWN_BLOCK_SIZE_ATTRS]] = { "amdgpu-flat-work-group-size"="128,128"
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