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[RISCV] Set riscv-fpimm-cost threshold to 3 by default #159352

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Merged
merged 3 commits into from
Sep 24, 2025
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[RISCV] Set riscv-fpimm-cost threshold to 3 by default #159352

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335f2ff
[RISCV] Set riscv-fpimm-cost threshold to 3 by default
asb Sep 17, 2025
efc9b03
Merge remote-tracking branch 'origin/main' into 2025q3-riscv-fp-imm-c…
asb Sep 22, 2025
b19e08b
Merge remote-tracking branch 'origin/main' into 2025q3-riscv-fp-imm-c…
asb Sep 24, 2025
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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -79,7 +79,7 @@ static cl::opt<int>
FPImmCost(DEBUG_TYPE "-fpimm-cost", cl::Hidden,
cl::desc("Give the maximum number of instructions that we will "
"use for creating a floating-point immediate value"),
cl::init(2));
cl::init(3));
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I was thinking why we can't just use RISCVSubtarget::getMaxBuildIntsCost() - 1 (minus 1 because we need a conversion from int to float)?

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We'd need to account for Zfinx/Zdinx as well which doesn't need the conversion. I see this as a good suggestion for what a more "principled" constant to use might be, which might be worth exploring as a followup.


static cl::opt<bool>
ReassocShlAddiAdd("reassoc-shl-addi-add", cl::Hidden,
Expand Down
219 changes: 130 additions & 89 deletions llvm/test/CodeGen/RISCV/bfloat-convert.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -51,13 +51,14 @@ define i16 @fcvt_si_bf16_sat(bfloat %a) nounwind {
; CHECK32ZFBFMIN-LABEL: fcvt_si_bf16_sat:
; CHECK32ZFBFMIN: # %bb.0: # %start
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK32ZFBFMIN-NEXT: lui a0, %hi(.LCPI1_0)
; CHECK32ZFBFMIN-NEXT: feq.s a1, fa5, fa5
; CHECK32ZFBFMIN-NEXT: flw fa4, %lo(.LCPI1_0)(a0)
; CHECK32ZFBFMIN-NEXT: lui a0, 815104
; CHECK32ZFBFMIN-NEXT: fmv.w.x fa3, a0
; CHECK32ZFBFMIN-NEXT: fmax.s fa5, fa5, fa3
; CHECK32ZFBFMIN-NEXT: neg a0, a1
; CHECK32ZFBFMIN-NEXT: lui a1, 290816
; CHECK32ZFBFMIN-NEXT: fmv.w.x fa4, a0
; CHECK32ZFBFMIN-NEXT: feq.s a0, fa5, fa5
; CHECK32ZFBFMIN-NEXT: addi a1, a1, -512
; CHECK32ZFBFMIN-NEXT: neg a0, a0
; CHECK32ZFBFMIN-NEXT: fmax.s fa5, fa5, fa4
; CHECK32ZFBFMIN-NEXT: fmv.w.x fa4, a1
; CHECK32ZFBFMIN-NEXT: fmin.s fa5, fa5, fa4
; CHECK32ZFBFMIN-NEXT: fcvt.w.s a1, fa5, rtz
; CHECK32ZFBFMIN-NEXT: and a0, a0, a1
Expand All @@ -68,12 +69,13 @@ define i16 @fcvt_si_bf16_sat(bfloat %a) nounwind {
; RV32ID-NEXT: fmv.x.w a0, fa0
; RV32ID-NEXT: lui a1, 815104
; RV32ID-NEXT: fmv.w.x fa5, a1
; RV32ID-NEXT: lui a1, %hi(.LCPI1_0)
; RV32ID-NEXT: lui a1, 290816
; RV32ID-NEXT: slli a0, a0, 16
; RV32ID-NEXT: flw fa4, %lo(.LCPI1_0)(a1)
; RV32ID-NEXT: fmv.w.x fa3, a0
; RV32ID-NEXT: feq.s a0, fa3, fa3
; RV32ID-NEXT: fmax.s fa5, fa3, fa5
; RV32ID-NEXT: addi a1, a1, -512
; RV32ID-NEXT: fmv.w.x fa4, a0
; RV32ID-NEXT: feq.s a0, fa4, fa4
; RV32ID-NEXT: fmax.s fa5, fa4, fa5
; RV32ID-NEXT: fmv.w.x fa4, a1
; RV32ID-NEXT: neg a0, a0
; RV32ID-NEXT: fmin.s fa5, fa5, fa4
; RV32ID-NEXT: fcvt.w.s a1, fa5, rtz
Expand All @@ -83,13 +85,14 @@ define i16 @fcvt_si_bf16_sat(bfloat %a) nounwind {
; CHECK64ZFBFMIN-LABEL: fcvt_si_bf16_sat:
; CHECK64ZFBFMIN: # %bb.0: # %start
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK64ZFBFMIN-NEXT: lui a0, %hi(.LCPI1_0)
; CHECK64ZFBFMIN-NEXT: feq.s a1, fa5, fa5
; CHECK64ZFBFMIN-NEXT: flw fa4, %lo(.LCPI1_0)(a0)
; CHECK64ZFBFMIN-NEXT: lui a0, 815104
; CHECK64ZFBFMIN-NEXT: fmv.w.x fa3, a0
; CHECK64ZFBFMIN-NEXT: fmax.s fa5, fa5, fa3
; CHECK64ZFBFMIN-NEXT: neg a0, a1
; CHECK64ZFBFMIN-NEXT: lui a1, 290816
; CHECK64ZFBFMIN-NEXT: fmv.w.x fa4, a0
; CHECK64ZFBFMIN-NEXT: feq.s a0, fa5, fa5
; CHECK64ZFBFMIN-NEXT: addi a1, a1, -512
; CHECK64ZFBFMIN-NEXT: neg a0, a0
; CHECK64ZFBFMIN-NEXT: fmax.s fa5, fa5, fa4
; CHECK64ZFBFMIN-NEXT: fmv.w.x fa4, a1
; CHECK64ZFBFMIN-NEXT: fmin.s fa5, fa5, fa4
; CHECK64ZFBFMIN-NEXT: fcvt.l.s a1, fa5, rtz
; CHECK64ZFBFMIN-NEXT: and a0, a0, a1
Expand All @@ -100,12 +103,13 @@ define i16 @fcvt_si_bf16_sat(bfloat %a) nounwind {
; RV64ID-NEXT: fmv.x.w a0, fa0
; RV64ID-NEXT: lui a1, 815104
; RV64ID-NEXT: fmv.w.x fa5, a1
; RV64ID-NEXT: lui a1, %hi(.LCPI1_0)
; RV64ID-NEXT: lui a1, 290816
; RV64ID-NEXT: slli a0, a0, 16
; RV64ID-NEXT: flw fa4, %lo(.LCPI1_0)(a1)
; RV64ID-NEXT: fmv.w.x fa3, a0
; RV64ID-NEXT: feq.s a0, fa3, fa3
; RV64ID-NEXT: fmax.s fa5, fa3, fa5
; RV64ID-NEXT: addi a1, a1, -512
; RV64ID-NEXT: fmv.w.x fa4, a0
; RV64ID-NEXT: feq.s a0, fa4, fa4
; RV64ID-NEXT: fmax.s fa5, fa4, fa5
; RV64ID-NEXT: fmv.w.x fa4, a1
; RV64ID-NEXT: neg a0, a0
; RV64ID-NEXT: fmin.s fa5, fa5, fa4
; RV64ID-NEXT: fcvt.l.s a1, fa5, rtz
Expand Down Expand Up @@ -152,49 +156,53 @@ define i16 @fcvt_ui_bf16(bfloat %a) nounwind {
define i16 @fcvt_ui_bf16_sat(bfloat %a) nounwind {
; CHECK32ZFBFMIN-LABEL: fcvt_ui_bf16_sat:
; CHECK32ZFBFMIN: # %bb.0: # %start
; CHECK32ZFBFMIN-NEXT: lui a0, %hi(.LCPI3_0)
; CHECK32ZFBFMIN-NEXT: flw fa5, %lo(.LCPI3_0)(a0)
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa4, fa0
; CHECK32ZFBFMIN-NEXT: fmv.w.x fa3, zero
; CHECK32ZFBFMIN-NEXT: fmax.s fa4, fa4, fa3
; CHECK32ZFBFMIN-NEXT: fmin.s fa5, fa4, fa5
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK32ZFBFMIN-NEXT: fmv.w.x fa4, zero
; CHECK32ZFBFMIN-NEXT: lui a0, 292864
; CHECK32ZFBFMIN-NEXT: fmax.s fa5, fa5, fa4
; CHECK32ZFBFMIN-NEXT: addi a0, a0, -256
; CHECK32ZFBFMIN-NEXT: fmv.w.x fa4, a0
; CHECK32ZFBFMIN-NEXT: fmin.s fa5, fa5, fa4
; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
; CHECK32ZFBFMIN-NEXT: ret
;
; RV32ID-LABEL: fcvt_ui_bf16_sat:
; RV32ID: # %bb.0: # %start
; RV32ID-NEXT: lui a0, %hi(.LCPI3_0)
; RV32ID-NEXT: flw fa5, %lo(.LCPI3_0)(a0)
; RV32ID-NEXT: fmv.x.w a0, fa0
; RV32ID-NEXT: fmv.w.x fa5, zero
; RV32ID-NEXT: slli a0, a0, 16
; RV32ID-NEXT: fmv.w.x fa4, a0
; RV32ID-NEXT: fmv.w.x fa3, zero
; RV32ID-NEXT: fmax.s fa4, fa4, fa3
; RV32ID-NEXT: fmin.s fa5, fa4, fa5
; RV32ID-NEXT: lui a0, 292864
; RV32ID-NEXT: addi a0, a0, -256
; RV32ID-NEXT: fmax.s fa5, fa4, fa5
; RV32ID-NEXT: fmv.w.x fa4, a0
; RV32ID-NEXT: fmin.s fa5, fa5, fa4
; RV32ID-NEXT: fcvt.wu.s a0, fa5, rtz
; RV32ID-NEXT: ret
;
; CHECK64ZFBFMIN-LABEL: fcvt_ui_bf16_sat:
; CHECK64ZFBFMIN: # %bb.0: # %start
; CHECK64ZFBFMIN-NEXT: lui a0, %hi(.LCPI3_0)
; CHECK64ZFBFMIN-NEXT: flw fa5, %lo(.LCPI3_0)(a0)
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa4, fa0
; CHECK64ZFBFMIN-NEXT: fmv.w.x fa3, zero
; CHECK64ZFBFMIN-NEXT: fmax.s fa4, fa4, fa3
; CHECK64ZFBFMIN-NEXT: fmin.s fa5, fa4, fa5
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK64ZFBFMIN-NEXT: fmv.w.x fa4, zero
; CHECK64ZFBFMIN-NEXT: lui a0, 292864
; CHECK64ZFBFMIN-NEXT: fmax.s fa5, fa5, fa4
; CHECK64ZFBFMIN-NEXT: addi a0, a0, -256
; CHECK64ZFBFMIN-NEXT: fmv.w.x fa4, a0
; CHECK64ZFBFMIN-NEXT: fmin.s fa5, fa5, fa4
; CHECK64ZFBFMIN-NEXT: fcvt.lu.s a0, fa5, rtz
; CHECK64ZFBFMIN-NEXT: ret
;
; RV64ID-LABEL: fcvt_ui_bf16_sat:
; RV64ID: # %bb.0: # %start
; RV64ID-NEXT: lui a0, %hi(.LCPI3_0)
; RV64ID-NEXT: flw fa5, %lo(.LCPI3_0)(a0)
; RV64ID-NEXT: fmv.x.w a0, fa0
; RV64ID-NEXT: fmv.w.x fa5, zero
; RV64ID-NEXT: slli a0, a0, 16
; RV64ID-NEXT: fmv.w.x fa4, a0
; RV64ID-NEXT: fmv.w.x fa3, zero
; RV64ID-NEXT: fmax.s fa4, fa4, fa3
; RV64ID-NEXT: fmin.s fa5, fa4, fa5
; RV64ID-NEXT: lui a0, 292864
; RV64ID-NEXT: addi a0, a0, -256
; RV64ID-NEXT: fmax.s fa5, fa4, fa5
; RV64ID-NEXT: fmv.w.x fa4, a0
; RV64ID-NEXT: fmin.s fa5, fa5, fa4
; RV64ID-NEXT: fcvt.lu.s a0, fa5, rtz
; RV64ID-NEXT: ret
start:
Expand Down Expand Up @@ -472,20 +480,21 @@ define i64 @fcvt_l_bf16_sat(bfloat %a) nounwind {
; RV32IZFBFMIN-NEXT: # %bb.1: # %start
; RV32IZFBFMIN-NEXT: mv a2, a1
; RV32IZFBFMIN-NEXT: .LBB10_2: # %start
; RV32IZFBFMIN-NEXT: lui a1, %hi(.LCPI10_0)
; RV32IZFBFMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a1)
; RV32IZFBFMIN-NEXT: lui a1, 389120
; RV32IZFBFMIN-NEXT: addi a1, a1, -1
; RV32IZFBFMIN-NEXT: fmv.w.x fa5, a1
; RV32IZFBFMIN-NEXT: flt.s a1, fa5, fs0
; RV32IZFBFMIN-NEXT: beqz a1, .LBB10_4
; RV32IZFBFMIN-NEXT: # %bb.3:
; RV32IZFBFMIN-NEXT: addi a2, a3, -1
; RV32IZFBFMIN-NEXT: .LBB10_4: # %start
; RV32IZFBFMIN-NEXT: feq.s a3, fs0, fs0
; RV32IZFBFMIN-NEXT: neg a4, a1
; RV32IZFBFMIN-NEXT: neg a1, s0
; RV32IZFBFMIN-NEXT: neg a4, s0
; RV32IZFBFMIN-NEXT: neg a5, a1
; RV32IZFBFMIN-NEXT: neg a3, a3
; RV32IZFBFMIN-NEXT: and a0, a1, a0
; RV32IZFBFMIN-NEXT: and a0, a4, a0
; RV32IZFBFMIN-NEXT: and a1, a3, a2
; RV32IZFBFMIN-NEXT: or a0, a4, a0
; RV32IZFBFMIN-NEXT: or a0, a5, a0
; RV32IZFBFMIN-NEXT: and a0, a3, a0
; RV32IZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFBFMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
Expand All @@ -511,20 +520,21 @@ define i64 @fcvt_l_bf16_sat(bfloat %a) nounwind {
; R32IDZFBFMIN-NEXT: # %bb.1: # %start
; R32IDZFBFMIN-NEXT: mv a2, a1
; R32IDZFBFMIN-NEXT: .LBB10_2: # %start
; R32IDZFBFMIN-NEXT: lui a1, %hi(.LCPI10_0)
; R32IDZFBFMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a1)
; R32IDZFBFMIN-NEXT: lui a1, 389120
; R32IDZFBFMIN-NEXT: addi a1, a1, -1
; R32IDZFBFMIN-NEXT: fmv.w.x fa5, a1
; R32IDZFBFMIN-NEXT: flt.s a1, fa5, fs0
; R32IDZFBFMIN-NEXT: beqz a1, .LBB10_4
; R32IDZFBFMIN-NEXT: # %bb.3:
; R32IDZFBFMIN-NEXT: addi a2, a3, -1
; R32IDZFBFMIN-NEXT: .LBB10_4: # %start
; R32IDZFBFMIN-NEXT: feq.s a3, fs0, fs0
; R32IDZFBFMIN-NEXT: neg a4, a1
; R32IDZFBFMIN-NEXT: neg a1, s0
; R32IDZFBFMIN-NEXT: neg a4, s0
; R32IDZFBFMIN-NEXT: neg a5, a1
; R32IDZFBFMIN-NEXT: neg a3, a3
; R32IDZFBFMIN-NEXT: and a0, a1, a0
; R32IDZFBFMIN-NEXT: and a0, a4, a0
; R32IDZFBFMIN-NEXT: and a1, a3, a2
; R32IDZFBFMIN-NEXT: or a0, a4, a0
; R32IDZFBFMIN-NEXT: or a0, a5, a0
; R32IDZFBFMIN-NEXT: and a0, a3, a0
; R32IDZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; R32IDZFBFMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
Expand Down Expand Up @@ -552,8 +562,9 @@ define i64 @fcvt_l_bf16_sat(bfloat %a) nounwind {
; RV32ID-NEXT: # %bb.1: # %start
; RV32ID-NEXT: mv a2, a1
; RV32ID-NEXT: .LBB10_2: # %start
; RV32ID-NEXT: lui a1, %hi(.LCPI10_0)
; RV32ID-NEXT: flw fa5, %lo(.LCPI10_0)(a1)
; RV32ID-NEXT: lui a1, 389120
; RV32ID-NEXT: addi a1, a1, -1
; RV32ID-NEXT: fmv.w.x fa5, a1
; RV32ID-NEXT: flt.s a1, fa5, fs0
; RV32ID-NEXT: beqz a1, .LBB10_4
; RV32ID-NEXT: # %bb.3:
Expand Down Expand Up @@ -641,30 +652,59 @@ define i64 @fcvt_lu_bf16(bfloat %a) nounwind {
}

define i64 @fcvt_lu_bf16_sat(bfloat %a) nounwind {
; CHECK32ZFBFMIN-LABEL: fcvt_lu_bf16_sat:
; CHECK32ZFBFMIN: # %bb.0: # %start
; CHECK32ZFBFMIN-NEXT: addi sp, sp, -16
; CHECK32ZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK32ZFBFMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; CHECK32ZFBFMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; CHECK32ZFBFMIN-NEXT: lui a0, %hi(.LCPI12_0)
; CHECK32ZFBFMIN-NEXT: flw fa5, %lo(.LCPI12_0)(a0)
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa0, fa0
; CHECK32ZFBFMIN-NEXT: fmv.w.x fa4, zero
; CHECK32ZFBFMIN-NEXT: fle.s a0, fa4, fa0
; CHECK32ZFBFMIN-NEXT: flt.s a1, fa5, fa0
; CHECK32ZFBFMIN-NEXT: neg s0, a1
; CHECK32ZFBFMIN-NEXT: neg s1, a0
; CHECK32ZFBFMIN-NEXT: call __fixunssfdi
; CHECK32ZFBFMIN-NEXT: and a0, s1, a0
; CHECK32ZFBFMIN-NEXT: and a1, s1, a1
; CHECK32ZFBFMIN-NEXT: or a0, s0, a0
; CHECK32ZFBFMIN-NEXT: or a1, s0, a1
; CHECK32ZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK32ZFBFMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK32ZFBFMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; CHECK32ZFBFMIN-NEXT: addi sp, sp, 16
; CHECK32ZFBFMIN-NEXT: ret
; RV32IZFBFMIN-LABEL: fcvt_lu_bf16_sat:
; RV32IZFBFMIN: # %bb.0: # %start
; RV32IZFBFMIN-NEXT: addi sp, sp, -16
; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFBFMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZFBFMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fs0, fa0
; RV32IZFBFMIN-NEXT: fmv.w.x fa5, zero
; RV32IZFBFMIN-NEXT: fle.s a0, fa5, fs0
; RV32IZFBFMIN-NEXT: neg s0, a0
; RV32IZFBFMIN-NEXT: fmv.s fa0, fs0
; RV32IZFBFMIN-NEXT: call __fixunssfdi
; RV32IZFBFMIN-NEXT: and a0, s0, a0
; RV32IZFBFMIN-NEXT: lui a2, 391168
; RV32IZFBFMIN-NEXT: and a1, s0, a1
; RV32IZFBFMIN-NEXT: addi a2, a2, -1
; RV32IZFBFMIN-NEXT: fmv.w.x fa5, a2
; RV32IZFBFMIN-NEXT: flt.s a2, fa5, fs0
; RV32IZFBFMIN-NEXT: neg a2, a2
; RV32IZFBFMIN-NEXT: or a0, a2, a0
; RV32IZFBFMIN-NEXT: or a1, a2, a1
; RV32IZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFBFMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFBFMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFBFMIN-NEXT: addi sp, sp, 16
; RV32IZFBFMIN-NEXT: ret
;
; R32IDZFBFMIN-LABEL: fcvt_lu_bf16_sat:
; R32IDZFBFMIN: # %bb.0: # %start
; R32IDZFBFMIN-NEXT: addi sp, sp, -16
; R32IDZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; R32IDZFBFMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; R32IDZFBFMIN-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; R32IDZFBFMIN-NEXT: fcvt.s.bf16 fs0, fa0
; R32IDZFBFMIN-NEXT: fmv.w.x fa5, zero
; R32IDZFBFMIN-NEXT: fle.s a0, fa5, fs0
; R32IDZFBFMIN-NEXT: neg s0, a0
; R32IDZFBFMIN-NEXT: fmv.s fa0, fs0
; R32IDZFBFMIN-NEXT: call __fixunssfdi
; R32IDZFBFMIN-NEXT: and a0, s0, a0
; R32IDZFBFMIN-NEXT: lui a2, 391168
; R32IDZFBFMIN-NEXT: and a1, s0, a1
; R32IDZFBFMIN-NEXT: addi a2, a2, -1
; R32IDZFBFMIN-NEXT: fmv.w.x fa5, a2
; R32IDZFBFMIN-NEXT: flt.s a2, fa5, fs0
; R32IDZFBFMIN-NEXT: neg a2, a2
; R32IDZFBFMIN-NEXT: or a0, a2, a0
; R32IDZFBFMIN-NEXT: or a1, a2, a1
; R32IDZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; R32IDZFBFMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; R32IDZFBFMIN-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
; R32IDZFBFMIN-NEXT: addi sp, sp, 16
; R32IDZFBFMIN-NEXT: ret
;
; RV32ID-LABEL: fcvt_lu_bf16_sat:
; RV32ID: # %bb.0: # %start
Expand All @@ -673,15 +713,16 @@ define i64 @fcvt_lu_bf16_sat(bfloat %a) nounwind {
; RV32ID-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32ID-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32ID-NEXT: fmv.x.w a0, fa0
; RV32ID-NEXT: lui a1, %hi(.LCPI12_0)
; RV32ID-NEXT: fmv.w.x fa5, zero
; RV32ID-NEXT: flw fa4, %lo(.LCPI12_0)(a1)
; RV32ID-NEXT: lui a1, 391168
; RV32ID-NEXT: slli a0, a0, 16
; RV32ID-NEXT: addi a1, a1, -1
; RV32ID-NEXT: fmv.w.x fa0, a0
; RV32ID-NEXT: fle.s a0, fa5, fa0
; RV32ID-NEXT: flt.s a1, fa4, fa0
; RV32ID-NEXT: neg s0, a1
; RV32ID-NEXT: neg s1, a0
; RV32ID-NEXT: fmv.w.x fa5, a1
; RV32ID-NEXT: flt.s a0, fa5, fa0
; RV32ID-NEXT: fmv.w.x fa5, zero
; RV32ID-NEXT: fle.s a1, fa5, fa0
; RV32ID-NEXT: neg s0, a0
; RV32ID-NEXT: neg s1, a1
; RV32ID-NEXT: call __fixunssfdi
; RV32ID-NEXT: and a0, s1, a0
; RV32ID-NEXT: and a1, s1, a1
Expand Down
5 changes: 3 additions & 2 deletions llvm/test/CodeGen/RISCV/bfloat-imm.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -7,8 +7,9 @@
define bfloat @bfloat_imm() nounwind {
; CHECK-LABEL: bfloat_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
; CHECK-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
; CHECK-NEXT: lui a0, 4
; CHECK-NEXT: addi a0, a0, 64
; CHECK-NEXT: fmv.h.x fa0, a0
; CHECK-NEXT: ret
ret bfloat 3.0
}
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