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AMDGPU: Remove unnecessary operand legalization for WMMAs #159370

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Merged
merged 2 commits into from
Sep 18, 2025
Merged

AMDGPU: Remove unnecessary operand legalization for WMMAs #159370

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d837801
AMDGPU: Constrain regclass when replacing SGPRs with VGPRs
arsenm Sep 17, 2025
257ef69
AMDGPU: Remove unnecessary operand legalization for WMMAs
arsenm Sep 17, 2025
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20 changes: 4 additions & 16 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6547,21 +6547,6 @@ void SIInstrInfo::legalizeOperandsVOP3(MachineRegisterInfo &MRI,
!RI.isVGPR(MRI, MI.getOperand(VOP3Idx[2]).getReg()))
legalizeOpWithMove(MI, VOP3Idx[2]);

if (isWMMA(MI)) {
// scale_src has a register class restricted to low 256 VGPRs, we may need
// to insert a copy to the restricted VGPR class.
int ScaleSrc0Idx =
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::scale_src0);
if (ScaleSrc0Idx != -1) {
int ScaleSrc1Idx =
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::scale_src1);
if (!isOperandLegal(MI, ScaleSrc0Idx))
legalizeOpWithMove(MI, ScaleSrc0Idx);
if (!isOperandLegal(MI, ScaleSrc1Idx))
legalizeOpWithMove(MI, ScaleSrc1Idx);
}
}

// Fix the register class of packed FP32 instructions on gfx12+. See
// SIInstrInfo::isLegalGFX12PlusPackedMathFP32Operand for more information.
if (AMDGPU::isPackedFP32Inst(Opc) && AMDGPU::isGFX12Plus(ST)) {
Expand Down Expand Up @@ -8993,7 +8978,10 @@ void SIInstrInfo::addUsersToMoveToVALUWorklist(
break;
}

if (!RI.hasVectorRegisters(getOpRegClass(UseMI, OpNo)))
const TargetRegisterClass *OpRC = getOpRegClass(UseMI, OpNo);
MRI.constrainRegClass(DstReg, OpRC);

if (!RI.hasVectorRegisters(OpRC))
Worklist.insert(&UseMI);
else
// Legalization could change user list.
Expand Down