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[RISCV][NFC] Merge some WriteRes entries in SiFive7 scheduling model #159448

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Merged
merged 1 commit into from
Sep 17, 2025
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[RISCV][NFC] Merge some WriteRes entries in SiFive7 scheduling model #159448

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20 changes: 6 additions & 14 deletions llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
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Original file line number Diff line number Diff line change
Expand Up @@ -412,13 +412,9 @@ multiclass SiFive7WriteResBase<int VLEN,
def : WriteRes<WriteFMinMax32, [PipeB]>;
}

def : WriteRes<WriteFDiv32, [PipeB, FDiv]> {
let Latency = 27;
let ReleaseAtCycles = [1, 26];
}
def : WriteRes<WriteFSqrt32, [PipeB, FDiv]> {
let Latency = 27;
let ReleaseAtCycles = [1, 26];
let Latency = 27, ReleaseAtCycles = [1, 26] in {
def : WriteRes<WriteFDiv32, [PipeB, FDiv]>;
def : WriteRes<WriteFSqrt32, [PipeB, FDiv]>;
}

// Double precision
Expand All @@ -432,13 +428,9 @@ multiclass SiFive7WriteResBase<int VLEN,
def : WriteRes<WriteFMinMax64, [PipeB]>;
}

def : WriteRes<WriteFDiv64, [PipeB, FDiv]> {
let Latency = 56;
let ReleaseAtCycles = [1, 55];
}
def : WriteRes<WriteFSqrt64, [PipeB, FDiv]> {
let Latency = 56;
let ReleaseAtCycles = [1, 55];
let Latency = 56, ReleaseAtCycles = [1, 55] in {
def : WriteRes<WriteFDiv64, [PipeB, FDiv]>;
def : WriteRes<WriteFSqrt64, [PipeB, FDiv]>;
}

// Conversions
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