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[AMDGPU] gfx1251 VOP3 dpp support #159654

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Merged
merged 5 commits into from
Sep 18, 2025
Merged

[AMDGPU] gfx1251 VOP3 dpp support #159654

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dfcc9d2
[AMDGPU] gfx1251 VOP1 dpp support
rampitec Sep 18, 2025
344bfe1
[AMDGPU] gfx1251 VOP2 dpp support
rampitec Sep 18, 2025
ace386e
Merge branch 'main' into users/rampitec/09-18-_amdgpu_gfx1251_vop2_dp…
rampitec Sep 18, 2025
b83405b
[AMDGPU] gfx1251 VOP3 dpp support
rampitec Sep 18, 2025
4fa530d
Merge branch 'main' into users/rampitec/09-18-_amdgpu_gfx1251_vop3_dp…
rampitec Sep 18, 2025
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1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1969,6 +1969,7 @@ class getVOP3DPPSrcForVT<ValueType VT, bit IsFake16 = 1> {
RegisterOperand ret =
!cond(!eq(VT, i1) : SSrc_i1,
!eq(VT, i16) : !if (IsFake16, VCSrc_b16, VCSrcT_b16),
!eq(VT, i64) : VCSrc_b64,
!eq(VT, f16) : !if (IsFake16, VCSrc_f16, VCSrcT_f16),
!eq(VT, bf16) : !if (IsFake16, VCSrc_bf16, VCSrcT_bf16),
!eq(VT, v2i16) : VCSrc_v2b16,
Expand Down
79 changes: 45 additions & 34 deletions llvm/lib/Target/AMDGPU/VOP2Instructions.td
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Expand Up @@ -287,10 +287,14 @@ multiclass VOP2bInst <string opName,
def _e64 : VOP3InstBase <opName, P, node, 1>,
Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;

let SubtargetPredicate = isGFX11Plus in {
if P.HasExtVOP3DPP then
def _e64_dpp : VOP3_DPP_Pseudo <opName, P>;
} // End SubtargetPredicate = isGFX11Plus
if P.HasExtVOP3DPP then
def _e64_dpp : VOP3_DPP_Pseudo <opName, P> {
let SubtargetPredicate = isGFX11Plus;
}
else if P.HasExt64BitDPP then
def _e64_dpp : VOP3_DPP_Pseudo <opName, P> {
let OtherPredicates = [HasDPALU_DPP];
}
}
}

Expand Down Expand Up @@ -345,10 +349,14 @@ multiclass
VOPD_Component<VOPDOp, VOPDName>;
}

let SubtargetPredicate = isGFX11Plus in {
if P.HasExtVOP3DPP then
def _e64_dpp : VOP3_DPP_Pseudo <opName, P>;
} // End SubtargetPredicate = isGFX11Plus
if P.HasExtVOP3DPP then
def _e64_dpp : VOP3_DPP_Pseudo <opName, P> {
let SubtargetPredicate = isGFX11Plus;
}
else if P.HasExt64BitDPP then
def _e64_dpp : VOP3_DPP_Pseudo <opName, P> {
let OtherPredicates = [HasDPALU_DPP];
}
}
}

Expand Down Expand Up @@ -1607,8 +1615,9 @@ multiclass VOP2_Real_dpp<GFXGen Gen, bits<6> op> {
}

multiclass VOP2_Real_dpp8<GFXGen Gen, bits<6> op> {
if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then
def _dpp8#Gen.Suffix : VOP2_DPP8_Gen<op, !cast<VOP2_Pseudo>(NAME#"_e32"), Gen>;
defvar ps = !cast<VOP2_Pseudo>(NAME#"_e32");
if !and(ps.Pfl.HasExtDPP, !not(ps.Pfl.HasExt64BitDPP)) then
def _dpp8#Gen.Suffix : VOP2_DPP8_Gen<op, ps, Gen>;
}

//===------------------------- VOP2 (with name) -------------------------===//
Expand Down Expand Up @@ -1643,10 +1652,10 @@ multiclass VOP2_Real_dpp_with_name<GFXGen Gen, bits<6> op, string opName,
multiclass VOP2_Real_dpp8_with_name<GFXGen Gen, bits<6> op, string opName,
string asmName> {
defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");
if ps.Pfl.HasExtDPP then
def _dpp8#Gen.Suffix : VOP2_DPP8_Gen<op, ps, Gen> {
let AsmString = asmName # ps.Pfl.AsmDPP8;
}
if !and(ps.Pfl.HasExtDPP, !not(ps.Pfl.HasExt64BitDPP)) then
def _dpp8#Gen.Suffix : VOP2_DPP8_Gen<op, ps, Gen> {
let AsmString = asmName # ps.Pfl.AsmDPP8;
}
}

//===------------------------------ VOP2be ------------------------------===//
Expand Down Expand Up @@ -1687,32 +1696,32 @@ multiclass VOP2be_Real_dpp<GFXGen Gen, bits<6> op, string opName, string asmName
}
}
multiclass VOP2be_Real_dpp8<GFXGen Gen, bits<6> op, string opName, string asmName> {
if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then
defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");
if !and(ps.Pfl.HasExtDPP, !not(ps.Pfl.HasExt64BitDPP)) then {
def _dpp8#Gen.Suffix :
VOP2_DPP8_Gen<op, !cast<VOP2_Pseudo>(opName#"_e32"), Gen> {
string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
VOP2_DPP8_Gen<op, ps, Gen> {
string AsmDPP8 = ps.Pfl.AsmDPP8;
let AsmString = asmName # !subst(", vcc", "", AsmDPP8);
}
if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then
def _dpp8_w32#Gen.Suffix :
VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {
string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
VOP2_DPP8<op, ps> {
string AsmDPP8 = ps.Pfl.AsmDPP8;
let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP8);
let isAsmParserOnly = 1;
let WaveSizePredicate = isWave32;
let AssemblerPredicate = Gen.AssemblerPredicate;
let DecoderNamespace = Gen.DecoderNamespace;
}
if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then
def _dpp8_w64#Gen.Suffix :
VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {
string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
VOP2_DPP8<op, ps> {
string AsmDPP8 = ps.Pfl.AsmDPP8;
let AsmString = asmName # AsmDPP8;
let isAsmParserOnly = 1;
let WaveSizePredicate = isWave64;
let AssemblerPredicate = Gen.AssemblerPredicate;
let DecoderNamespace = Gen.DecoderNamespace;
}
}
}

// We don't want to override separate decoderNamespaces within these
Expand Down Expand Up @@ -1777,9 +1786,11 @@ multiclass VOP2_Real_NO_DPP_with_name<GFXGen Gen, bits<6> op, string opName,
}
}

multiclass VOP2_Real_NO_DPP_with_alias<GFXGen Gen, bits<6> op, string alias> {
multiclass VOP2_Real_with_DPP16_with_alias<GFXGen Gen, bits<6> op, string alias> {
defm NAME : VOP2_Real_e32<Gen, op>,
VOP2_Real_e64<Gen, op>;
VOP2_Real_dpp<Gen, op>,
VOP2_Real_e64<Gen, op>,
VOP3_Real_dpp_Base<Gen, {0, 1, 0, 0, op{5-0}}>;
def Gen.Suffix#"_alias" : AMDGPUMnemonicAlias<alias, NAME> {
let AssemblerPredicate = Gen.AssemblerPredicate;
}
Expand Down Expand Up @@ -1808,6 +1819,9 @@ multiclass VOP2_Real_FULL_t16_gfx12<bits<6> op, string opName,
}
}

multiclass VOP2_Real_with_DPP16_with_alias_gfx12<bits<6> op, string alias> :
VOP2_Real_with_DPP16_with_alias<GFX12Gen, op, alias>;

multiclass VOP2_Real_FULL_t16_and_fake16_gfx12<bits<6> op, string opName,
string asmName, string alias> {
defm _t16: VOP2_Real_FULL_t16_gfx12<op, opName#"_t16", asmName, alias>;
Expand All @@ -1818,14 +1832,11 @@ multiclass VOP2_Real_NO_DPP_with_name_gfx12<bits<6> op, string opName,
string asmName> :
VOP2_Real_NO_DPP_with_name<GFX12Gen, op, opName, asmName>;

multiclass VOP2_Real_NO_DPP_with_alias_gfx12<bits<6> op, string alias> :
VOP2_Real_NO_DPP_with_alias<GFX12Gen, op, alias>;

defm V_ADD_F64 : VOP2_Real_NO_DPP_with_name_gfx12<0x002, "V_ADD_F64_pseudo", "v_add_f64">;
defm V_MUL_F64 : VOP2_Real_NO_DPP_with_name_gfx12<0x006, "V_MUL_F64_pseudo", "v_mul_f64">;
defm V_LSHLREV_B64 : VOP2_Real_NO_DPP_with_name_gfx12<0x01f, "V_LSHLREV_B64_pseudo", "v_lshlrev_b64">;
defm V_MIN_NUM_F64 : VOP2_Real_NO_DPP_with_alias_gfx12<0x00d, "v_min_f64">;
defm V_MAX_NUM_F64 : VOP2_Real_NO_DPP_with_alias_gfx12<0x00e, "v_max_f64">;
defm V_ADD_F64 : VOP2_Real_FULL_with_name_gfx12<0x002, "V_ADD_F64_pseudo", "v_add_f64">;
defm V_MUL_F64 : VOP2_Real_FULL_with_name_gfx12<0x006, "V_MUL_F64_pseudo", "v_mul_f64">;
defm V_LSHLREV_B64 : VOP2_Real_FULL_with_name_gfx12<0x01f, "V_LSHLREV_B64_pseudo", "v_lshlrev_b64">;
defm V_MIN_NUM_F64 : VOP2_Real_with_DPP16_with_alias_gfx12<0x00d, "v_min_f64">;
defm V_MAX_NUM_F64 : VOP2_Real_with_DPP16_with_alias_gfx12<0x00e, "v_max_f64">;

defm V_CNDMASK_B32 : VOP2e_Real_gfx12<0x001, "V_CNDMASK_B32", "v_cndmask_b32">;
defm V_ADD_CO_CI_U32 :
Expand Down Expand Up @@ -2776,7 +2787,7 @@ let DecoderNamespace = "GFX90A" in {
}
} // End AssemblerPredicate = isGFX90APlus, DecoderNamespace = "GFX90A"

let SubtargetPredicate = HasFmacF64Inst in {
let SubtargetPredicate = HasFmacF64Inst, OtherPredicates = [isGFX9Only] in {
defm V_FMAC_F64 : VOP2_Real_e32e64_gfx90a <0x4>;
} // End SubtargetPredicate = HasFmacF64Inst

Expand Down
64 changes: 48 additions & 16 deletions llvm/lib/Target/AMDGPU/VOP3Instructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,7 @@ def VOP_F32_F32_F32_F32_VCC : VOPProfile<[f32, f32, f32, f32]> {
}
def VOP_F64_F64_F64_F64_VCC : VOPProfile<[f64, f64, f64, f64]> {
let Outs64 = (outs DstRC.RegClass:$vdst);
let HasExt64BitDPP = 1;
let IsSingle = 1;
}
}
Expand Down Expand Up @@ -51,7 +52,24 @@ def VOP3b_I64_I1_I32_I32_I64 : VOPProfile<[i64, i32, i32, i64]> {

let HasExt64BitDPP = 1 in {
def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile<f32>;
def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64>;
def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64> {
let OutsVOP3DPP = Outs64;
let AsmVOP3DPP = getAsmVOP3DPP<Asm64>.ret;
let AsmVOP3DPP16 = getAsmVOP3DPP16<Asm64>.ret;
let AsmVOP3DPP8 = getAsmVOP3DPP8<Asm64>.ret;
}

def VOP3b_I64_I1_I32_I32_I64_DPP : VOPProfile<[i64, i32, i32, i64]> {
let HasClamp = 1;

let IsSingle = 1;
let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
let OutsVOP3DPP = Outs64;
let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp";
let AsmVOP3DPP = getAsmVOP3DPP<Asm64>.ret;
let AsmVOP3DPP16 = getAsmVOP3DPP16<Asm64>.ret;
let AsmVOP3DPP8 = getAsmVOP3DPP8<Asm64>.ret;
}

class V_MUL_PROF<VOPProfile P> : VOP3_Profile<P> {
let HasExtVOP3DPP = 0;
Expand Down Expand Up @@ -229,7 +247,7 @@ defm V_DIV_FMAS_F32 : VOP3Inst_Pseudo_Wrapper <"v_div_fmas_f32", VOP_F32_F32_F32
// result *= 2^64
//
let SchedRW = [WriteDouble], FPDPRounding = 1 in
defm V_DIV_FMAS_F64 : VOP3Inst_Pseudo_Wrapper <"v_div_fmas_f64", VOP_F64_F64_F64_F64_VCC, []>;
defm V_DIV_FMAS_F64 : VOP3Inst <"v_div_fmas_f64", VOP_F64_F64_F64_F64_VCC>;
} // End Uses = [MODE, VCC, EXEC]

} // End isCommutable = 1
Expand Down Expand Up @@ -294,7 +312,7 @@ defm V_CVT_PK_U8_F32 : VOP3Inst<"v_cvt_pk_u8_f32", VOP3_Profile<VOP_I32_F32_I32_
defm V_DIV_FIXUP_F32 : VOP3Inst <"v_div_fixup_f32", DIV_FIXUP_F32_PROF, AMDGPUdiv_fixup>;

let SchedRW = [WriteDoubleAdd], FPDPRounding = 1 in {
defm V_DIV_FIXUP_F64 : VOP3Inst <"v_div_fixup_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, AMDGPUdiv_fixup>;
defm V_DIV_FIXUP_F64 : VOP3Inst <"v_div_fixup_f64", VOP_F64_F64_F64_F64_DPP_PROF, AMDGPUdiv_fixup>;
defm V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64", VOP3_Profile<VOP_F64_F64_I32>, any_fldexp>;
} // End SchedRW = [WriteDoubleAdd], FPDPRounding = 1
} // End isReMaterializable = 1
Expand Down Expand Up @@ -335,7 +353,7 @@ let mayRaiseFPException = 0 in { // Seems suspicious but manual doesn't say it d

// Double precision division pre-scale.
let SchedRW = [WriteDouble, WriteSALU], FPDPRounding = 1 in
defm V_DIV_SCALE_F64 : VOP3Inst_Pseudo_Wrapper <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64>;
defm V_DIV_SCALE_F64 : VOP3Inst <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64>;
} // End mayRaiseFPException = 0

let isReMaterializable = 1 in
Expand Down Expand Up @@ -408,9 +426,9 @@ defm V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOPProfileMQSAD>;
} // End SubtargetPredicate = isGFX7Plus

let isCommutable = 1, SchedRW = [WriteIntMul, WriteSALU] in {
let SubtargetPredicate = isGFX7Plus, OtherPredicates = [HasNotMADIntraFwdBug] in {
defm V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64>;
defm V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>;
let SubtargetPredicate = isGFX7Plus in {
defm V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64_DPP, null_frag, [HasNotMADIntraFwdBug]>;
defm V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64_DPP, null_frag, [HasNotMADIntraFwdBug]>;
}
let SubtargetPredicate = isGFX11Only, OtherPredicates = [HasMADIntraFwdBug],
Constraints = "@earlyclobber $vdst" in {
Expand Down Expand Up @@ -2054,8 +2072,8 @@ defm V_S_SQRT_F32 : VOP3Only_Real_Base_gfx12<0x288>;
defm V_S_SQRT_F16 : VOP3Only_Real_Base_gfx12<0x289>;
defm V_MAD_CO_U64_U32 : VOP3be_Real_with_name_gfx12<0x2fe, "V_MAD_U64_U32", "v_mad_co_u64_u32">;
defm V_MAD_CO_I64_I32 : VOP3be_Real_with_name_gfx12<0x2ff, "V_MAD_I64_I32", "v_mad_co_i64_i32">;
defm V_MINIMUM_F64 : VOP3Only_Real_Base_gfx12<0x341>;
defm V_MAXIMUM_F64 : VOP3Only_Real_Base_gfx12<0x342>;
defm V_MINIMUM_F64 : VOP3Only_Realtriple_gfx11_gfx12<0x341>;
defm V_MAXIMUM_F64 : VOP3Only_Realtriple_gfx11_gfx12<0x342>;
defm V_MINIMUM_F32 : VOP3Only_Realtriple_gfx12<0x365>;
defm V_MAXIMUM_F32 : VOP3Only_Realtriple_gfx12<0x366>;
defm V_MINIMUM_F16 : VOP3Only_Realtriple_t16_and_fake16_gfx12<0x367, "v_minimum_f16">;
Expand Down Expand Up @@ -2127,6 +2145,13 @@ multiclass VOP3be_Real_gfx11_gfx12<bits<10> op, string opName, string asmName> :
VOP3be_Real<GFX11Gen, op, opName, asmName>,
VOP3be_Real<GFX12Gen, op, opName, asmName>;

multiclass VOP3be_Real_gfx11_gfx12_not_gfx1250<bits<10> op, string opName, string asmName> :
VOP3be_Real<GFX11Gen, op, opName, asmName>,
VOP3be_Real<GFX12Not12_50Gen, op, opName, asmName>;

multiclass VOP3be_Realtriple_gfx1250<bits<10> op> :
VOP3be_Realtriple<GFX1250Gen, op>;

multiclass VOP3_Real_No_Suffix_gfx11_gfx12<bits<10> op> :
VOP3_Real_No_Suffix<GFX11Gen, op>, VOP3_Real_No_Suffix<GFX12Gen, op>;

Expand All @@ -2141,7 +2166,7 @@ defm V_BFE_U32 : VOP3_Realtriple_gfx11_gfx12<0x210>;
defm V_BFE_I32 : VOP3_Realtriple_gfx11_gfx12<0x211>;
defm V_BFI_B32 : VOP3_Realtriple_gfx11_gfx12<0x212>;
defm V_FMA_F32 : VOP3_Realtriple_gfx11_gfx12<0x213>;
defm V_FMA_F64 : VOP3_Real_Base_gfx11_gfx12<0x214>;
defm V_FMA_F64 : VOP3_Real_Base_gfx11_gfx12_not_gfx1250<0x214>;
defm V_LERP_U8 : VOP3_Realtriple_gfx11_gfx12<0x215>;
defm V_ALIGNBIT_B32 : VOP3_Realtriple_t16_and_fake16_gfx11_gfx12<0x216, "v_alignbit_b32">;
defm V_ALIGNBYTE_B32 : VOP3_Realtriple_t16_and_fake16_gfx11_gfx12<0x217, "v_alignbyte_b32">;
Expand All @@ -2161,9 +2186,9 @@ defm V_SAD_U16 : VOP3_Realtriple_gfx11_gfx12<0x224>;
defm V_SAD_U32 : VOP3_Realtriple_gfx11_gfx12<0x225>;
defm V_CVT_PK_U8_F32 : VOP3_Realtriple_gfx11_gfx12<0x226>;
defm V_DIV_FIXUP_F32 : VOP3_Real_Base_gfx11_gfx12<0x227>;
defm V_DIV_FIXUP_F64 : VOP3_Real_Base_gfx11_gfx12<0x228>;
defm V_DIV_FIXUP_F64 : VOP3_Real_Base_gfx11_gfx12_not_gfx1250<0x228>;
defm V_DIV_FMAS_F32 : VOP3_Real_Base_gfx11_gfx12<0x237>;
defm V_DIV_FMAS_F64 : VOP3_Real_Base_gfx11_gfx12<0x238>;
defm V_DIV_FMAS_F64 : VOP3_Real_Base_gfx11_gfx12_not_gfx1250<0x238>;
defm V_MSAD_U8 : VOP3_Realtriple_gfx11_gfx12<0x239>;
defm V_QSAD_PK_U16_U8 : VOP3_Real_Base_gfx11_gfx12<0x23a>;
defm V_MQSAD_PK_U16_U8 : VOP3_Real_Base_gfx11_gfx12<0x23b>;
Expand Down Expand Up @@ -2205,7 +2230,7 @@ defm V_MINMAX_I32 : VOP3_Realtriple_gfx11_gfx12<0x265>;
defm V_DOT2_F16_F16 : VOP3Dot_Realtriple_t16_and_fake16_gfx11_gfx12<0x266, "v_dot2_f16_f16">;
defm V_DOT2_BF16_BF16 : VOP3Dot_Realtriple_t16_and_fake16_gfx11_gfx12<0x267, "v_dot2_bf16_bf16">;
defm V_DIV_SCALE_F32 : VOP3be_Real_gfx11_gfx12<0x2fc, "V_DIV_SCALE_F32", "v_div_scale_f32">;
defm V_DIV_SCALE_F64 : VOP3be_Real_gfx11_gfx12<0x2fd, "V_DIV_SCALE_F64", "v_div_scale_f64">;
defm V_DIV_SCALE_F64 : VOP3be_Real_gfx11_gfx12_not_gfx1250<0x2fd, "V_DIV_SCALE_F64", "v_div_scale_f64">;
defm V_MAD_U64_U32_gfx11 : VOP3be_Real_gfx11<0x2fe, "V_MAD_U64_U32_gfx11", "v_mad_u64_u32">;
defm V_MAD_I64_I32_gfx11 : VOP3be_Real_gfx11<0x2ff, "V_MAD_I64_I32_gfx11", "v_mad_i64_i32">;
defm V_ADD_NC_U16 : VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12<0x303, "v_add_nc_u16">;
Expand All @@ -2228,7 +2253,7 @@ defm V_ADD_F64 : VOP3_Real_Base_gfx11<0x327>;
defm V_MUL_F64 : VOP3_Real_Base_gfx11<0x328>;
defm V_MIN_F64 : VOP3_Real_Base_gfx11<0x329>;
defm V_MAX_F64 : VOP3_Real_Base_gfx11<0x32a>;
defm V_LDEXP_F64 : VOP3_Real_Base_gfx11_gfx12<0x32b>;
defm V_LDEXP_F64 : VOP3_Real_Base_gfx11_gfx12_not_gfx1250<0x32b>;
defm V_MUL_LO_U32 : VOP3_Real_Base_gfx11_gfx12_not_gfx1250<0x32c>;
defm V_MUL_HI_U32 : VOP3_Real_Base_gfx11_gfx12_not_gfx1250<0x32d>;
defm V_MUL_HI_I32 : VOP3_Real_Base_gfx11_gfx12_not_gfx1250<0x32e>;
Expand All @@ -2237,8 +2262,8 @@ defm V_LSHLREV_B16 : VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12<0x33
defm V_LSHRREV_B16 : VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12<0x339, "v_lshrrev_b16">;
defm V_ASHRREV_I16 : VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12<0x33a, "v_ashrrev_i16">;
defm V_LSHLREV_B64 : VOP3_Real_Base_gfx11<0x33c>;
defm V_LSHRREV_B64 : VOP3_Real_Base_gfx11_gfx12<0x33d>;
defm V_ASHRREV_I64 : VOP3_Real_Base_gfx11_gfx12<0x33e>;
defm V_LSHRREV_B64 : VOP3_Real_Base_gfx11_gfx12_not_gfx1250<0x33d>;
defm V_ASHRREV_I64 : VOP3_Real_Base_gfx11_gfx12_not_gfx1250<0x33e>;
defm V_READLANE_B32 : VOP3_Real_No_Suffix_gfx11_gfx12<0x360>; // Pseudo in VOP2
let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in {
defm V_WRITELANE_B32 : VOP3_Real_No_Suffix_gfx11_gfx12<0x361>; // Pseudo in VOP2
Expand All @@ -2260,9 +2285,16 @@ let AssemblerPredicate = isGFX11Plus in {
}

// These instructions differ from GFX12 variant by supporting DPP:
defm V_FMA_F64 : VOP3Only_Realtriple_gfx1250<0x214>;
defm V_DIV_FIXUP_F64 : VOP3Only_Realtriple_gfx1250<0x228>;
defm V_DIV_FMAS_F64 : VOP3Only_Realtriple_gfx1250<0x238>;
defm V_DIV_SCALE_F64 : VOP3be_Realtriple_gfx1250<0x2fd>;
defm V_LDEXP_F64 : VOP3Only_Realtriple_gfx1250<0x32b>;
defm V_MUL_LO_U32 : VOP3Only_Realtriple_gfx1250<0x32c>;
defm V_MUL_HI_U32 : VOP3Only_Realtriple_gfx1250<0x32d>;
defm V_MUL_HI_I32 : VOP3Only_Realtriple_gfx1250<0x32e>;
defm V_LSHRREV_B64 : VOP3Only_Realtriple_gfx1250<0x33d>;
defm V_ASHRREV_I64 : VOP3Only_Realtriple_gfx1250<0x33e>;

defm V_PERM_PK16_B4_U4 : VOP3Only_Real_Base_gfx1250<0x23f>;
defm V_PERM_PK16_B6_U4 : VOP3Only_Real_Base_gfx1250<0x242>;
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