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[AMDGPU][GlobalISel] Add regbankselect rules for G_FSHR #159818

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Merged
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Nov 19, 2025
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[AMDGPU][GlobalISel] Add regbankselect rules for G_FSHR #159818

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4 changes: 4 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -526,6 +526,10 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}})
.Div(S64, {{Vgpr64}, {Vgpr64, Vgpr32}});

addRulesForGOpcs({G_FSHR}, Standard)
.Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32, Vgpr32}})
.Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32, Vgpr32}});

addRulesForGOpcs({G_FRAME_INDEX}).Any({{UniP5, _}, {{SgprP5}, {None}}});

addRulesForGOpcs({G_UBFX, G_SBFX}, Standard)
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35 changes: 35 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll
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@@ -0,0 +1,35 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 < %s | FileCheck %s

define amdgpu_ps void @uniform_fshr_i32(i32 inreg %lhs, i32 inreg %rhs, i32 inreg %amt, ptr %resptr) {
; CHECK-LABEL: uniform_fshr_i32:
; CHECK: ; %bb.0:
; CHECK-NEXT: v_mov_b32_e32 v2, s2
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; CHECK-NEXT: v_alignbit_b32 v2, s0, s1, v2
; CHECK-NEXT: v_readfirstlane_b32 s0, v2
; CHECK-NEXT: s_add_co_i32 s0, s0, s0
; CHECK-NEXT: s_wait_alu 0xfffe
; CHECK-NEXT: v_mov_b32_e32 v2, s0
; CHECK-NEXT: flat_store_b32 v[0:1], v2
; CHECK-NEXT: s_endpgm
%vres = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 %amt)
%add = add i32 %vres, %vres
store i32 %add, ptr %resptr
ret void
}

declare i32 @llvm.amdgcn.readfirstlane.i32(i32)

define amdgpu_ps void @divergent_fshr_i32(i32 %lhs, i32 %rhs, i32 %amt, ptr %resptr) {
; CHECK-LABEL: divergent_fshr_i32:
; CHECK: ; %bb.0:
; CHECK-NEXT: v_alignbit_b32 v0, v0, v1, v2
; CHECK-NEXT: flat_store_b32 v[3:4], v0
; CHECK-NEXT: s_endpgm
%result = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 %amt)
store i32 %result, ptr %resptr
ret void
}

declare i32 @llvm.fshr.i32(i32, i32, i32)
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