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68 changes: 67 additions & 1 deletion mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
Original file line number Diff line number Diff line change
Expand Up @@ -112,6 +112,72 @@ def AMDGPU_ExtPackedFp8Op :
}];
}

def IsValidBlockSize: AttrConstraint<
CPred<"::llvm::cast<::mlir::IntegerAttr>($_self).getInt() == 16 || ::llvm::cast<::mlir::IntegerAttr>($_self).getInt() == 32">,
"whose value is 16 or 32">;

def AMDGPU_ScaledExtPacked816Op
: AMDGPU_Op<"scaled_ext_packed816", [Pure, TypesMatchWith<"scale type is fixed",
"source", "scale",
"ScaledExtPacked816Op::getScaleType($_self.getContext())">]>,
Arguments<(
ins AnyTypeOf<[VectorOfLengthAndType<[8], [F4E2M1FN,F8E4M3FN,F8E5M2]>,
VectorOfLengthAndType<[16], [F6E2M3FN, F6E3M2FN]>]>:$source,
FixedVectorOfLengthAndType<[4], [F8E8M0FNU]>:$scale,
ConfinedAttr<I32Attr, [IsValidBlockSize]>:$blockSize,
ConfinedAttr<I32Attr, [IntMinValue<0>, IntMaxValue<1>]>:$firstScaleLane,
ConfinedAttr<I32Attr, [IntMinValue<0>, IntMaxValue<2>]>:$firstScaleByte)>,
Results<(
outs AnyTypeOf<[FixedVectorOfLengthAndType<[8], [F32]>,
FixedVectorOfLengthAndType<[8], [F16]>,
FixedVectorOfLengthAndType<[8], [BF16]>,
FixedVectorOfLengthAndType<[16], [F32]>,
FixedVectorOfLengthAndType<[16], [F16]>,
FixedVectorOfLengthAndType<[16], [BF16]>]>:$res)> {

let summary = "Extend a vector of packed floating point values";

let description = [{
The scales applied to the input microfloats are stored in two bytes which
come from the `scales` input provided in a *half* of the wave identified
by `firstScaleLane`. The pair of bytes used is selected by
`firstScaleByte`. The 16 vectors in consecutive lanes starting from
`firstScaleLane` (which we'll call the scale vectors) will be used by both
halves of the wave (with lane L reading from L % 16'th scale vector), but
each half will use a different byte.

When the block size is 32, `firstScaleByte` can be either 0 or 2,
selecting halves of the scale vectors. Lanes 0-15 will read from
`firstScaleByte` and lanes 16-31 will read from `firstScaleByte` + 1.

However, when the block size is 16, `firstScaleByte` can be 0 or 1.
Lanes 0-15 read from the `firstScaleByte`th element of the scale vectors,
while lanes 16-31 read from `firstScaleByte` + 2.

Note: the layout for the scales generally mirrors how the WMMA
instructions use for matix scales. These selection operands allows
one to choose portions of the matrix to convert.

Available on gfx1250+.
}];

let assemblyFormat = [{
attr-dict $source
`scale` `(` $scale `)`
`blockSize` `(` $blockSize `)`
`firstScaleLane` `(` $firstScaleLane`)`
`firstScaleByte` `(` $firstScaleByte `)`
`:` type($source) `to` type($res)
}];

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Can you add a verifier that errors out on invalid block size / firstScaleByte combinations?

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Thanks for the review! 4f83cd9

let extraClassDeclaration = [{
static Type getScaleType(MLIRContext *ctx) {
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What's this for?

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I would like the assembly format to only have type($source) to type($res).

Without using

TypesMatchWith<"scale type is fixed",
                       "source", "scale",
                       "ScaledExtPacked816Op::getScaleType($_self.getContext())">]
// (which requires the definition of this extra class declaration)

The assembly format parser generator gives an error stating

error: type of operand #1, named 'scale', is not buildable and a buildable type cannot be inferred
    attr-dict $source

I can inline this function like this:

diff --git a/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td b/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
index 05525d3a061d..210097138807 100644
--- a/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
+++ b/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
@@ -119,7 +119,7 @@ def IsValidBlockSize: AttrConstraint<
 def AMDGPU_ScaledExtPacked816Op
     : AMDGPU_Op<"scaled_ext_packed816", [Pure, TypesMatchWith<"scale type is fixed",
                        "source", "scale",
-                       "ScaledExtPacked816Op::getScaleType($_self.getContext())">]>,
+                       "VectorType::get(4, Float8E8M0FNUType::get($_self.getContext()))">]>,
       Arguments<(
           ins AnyTypeOf<[VectorOfLengthAndType<[8], [F4E2M1FN,F8E4M3FN,F8E5M2]>,
                          VectorOfLengthAndType<[16], [F6E2M3FN, F6E3M2FN]>]>:$source,
@@ -170,12 +170,6 @@ def AMDGPU_ScaledExtPacked816Op
     `:` type($source) `to` type($res)
   }];

-  let extraClassDeclaration = [{
-    static Type getScaleType(MLIRContext *ctx) {
-      return VectorType::get(4, Float8E8M0FNUType::get(ctx));
-    }
-  }];
-
 }

 def AMDGPU_ScaledExtPackedOp

or if you prefer add the type declaration, or maybe another solution?

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  1. I don't think you want TypesMatchWith here - that implies a relationship between two types.
  2. What you're looking for goes something like this
def Vector4Scales : 
  AllOfType<[IsVectorOfShape<[4]>, IsVectorOfType<[F8E8M0FNU]>,
    "vector of 4 F8E8M0FNU scales",
    "::mlir::VectorType">,
  BuildableType<"::mlir::VectorType::get($_builder.getType<::mlir::Float8E8M0FNUType>, {4});">;

and then use that in the op definition

(See mlir/include/mlir/IR/CommonTypeConstraints.td for where all those tablegen bits came from.

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(The top half of that is defining the constraint the type has to obay. The BuildableType bit is a tag that tells the tablegen bits "Hey, this is one very specific type, you can just ... create it yourself and don't have to parse it".

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Thank you! I was looking for exactly this!

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Thanks for pointing into BuildableType. I had some issues using it exactly as you described above, but in the end I learned a little bit more about Predicates and Types. I ended up using the following:

def Vector4Scales :
  AllOfType<[FixedVectorOfLengthAndType<[4], [F8E8M0FNU]>],
    "vector of 4 F8E8M0FNU scales",
    "::mlir::VectorType">,
  BuildableType<"::mlir::VectorType::get({4}, $_builder.getType<::mlir::Float8E8M0FNUType>());">;

Which if I understand correctly the FixedVectorOfLEngthAndType should already take care of the constraints we need. (Instead of using/defining these constraints [IsVectorOfShape<[4]>, IsVectorOfType<[F8E8M0FNU]>) and adds the necessary BuildableType which I was missing.

return VectorType::get(4, Float8E8M0FNUType::get(ctx));
}
}];

}

def AMDGPU_ScaledExtPackedOp
: AMDGPU_Op<"scaled_ext_packed", [Pure]>,
Arguments<(
Expand Down Expand Up @@ -860,7 +926,7 @@ def AMDGPU_MFMAOp :
based on the provided `m`, `k`, `n`, and `nBlks` attributes, along with the
types of the source and destination arguments.

For information on the layouts of the input and output matrces (which are stored
For information on the layouts of the input and output matrices (which are stored
in `sourceA`, `sourceB`, `destC`, and `destD`), see the CDNA ISA documentation.

The `cbsz`, `abid`, and `blgp` parameters control how the lanes of the wave
Expand Down
55 changes: 55 additions & 0 deletions mlir/test/Dialect/AMDGPU/ops.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -221,6 +221,61 @@ func.func @scaled_ext_scalar_f4e2m1_bf16(%v: vector<2xf4E2M1FN>, %scale: f32) ->
func.return %ret : vector<2xbf16>
}

// CHECK-LABEL: func.func @scaled_ext_packed816_fp4
func.func @scaled_ext_packed816_fp4(%v: vector<8xf4E2M1FN>, %scale: vector<4xf8E8M0FNU>) -> (vector<8xf16>, vector<8xbf16>, vector<8xf32>) {
// CHECK: amdgpu.scaled_ext_packed816
%ret0 = amdgpu.scaled_ext_packed816 %v scale(%scale) blockSize(32) firstScaleLane(0) firstScaleByte(0) : vector<8xf4E2M1FN> to vector<8xf16>
// CHECK: amdgpu.scaled_ext_packed816
%ret1 = amdgpu.scaled_ext_packed816 %v scale(%scale) blockSize(32) firstScaleLane(0) firstScaleByte(0) : vector<8xf4E2M1FN> to vector<8xbf16>
// CHECK: amdgpu.scaled_ext_packed816
%ret2 = amdgpu.scaled_ext_packed816 %v scale(%scale) blockSize(32) firstScaleLane(0) firstScaleByte(0) : vector<8xf4E2M1FN> to vector<8xf32>
func.return %ret0, %ret1, %ret2 : vector<8xf16>, vector<8xbf16>, vector<8xf32>
}

// CHECK-LABEL: func.func @scaled_ext_packed816_fp8
func.func @scaled_ext_packed816_fp8(%v: vector<8xf8E4M3FN>, %scale: vector<4xf8E8M0FNU>) -> (vector<8xf16>, vector<8xbf16>, vector<8xf32>) {
// CHECK: amdgpu.scaled_ext_packed816
%ret0 = amdgpu.scaled_ext_packed816 %v scale(%scale) blockSize(32) firstScaleLane(0) firstScaleByte(0) : vector<8xf8E4M3FN> to vector<8xf16>
// CHECK: amdgpu.scaled_ext_packed816
%ret1 = amdgpu.scaled_ext_packed816 %v scale(%scale) blockSize(32) firstScaleLane(0) firstScaleByte(0) : vector<8xf8E4M3FN> to vector<8xbf16>
// CHECK: amdgpu.scaled_ext_packed816
%ret2 = amdgpu.scaled_ext_packed816 %v scale(%scale) blockSize(32) firstScaleLane(0) firstScaleByte(0) : vector<8xf8E4M3FN> to vector<8xf32>
func.return %ret0, %ret1, %ret2 : vector<8xf16>, vector<8xbf16>, vector<8xf32>
}

// CHECK-LABEL: func.func @scaled_ext_packed816_bf8
func.func @scaled_ext_packed816_bf8(%v: vector<8xf8E5M2>, %scale: vector<4xf8E8M0FNU>) -> (vector<8xf16>, vector<8xbf16>, vector<8xf32>) {
// CHECK: amdgpu.scaled_ext_packed816
%ret0 = amdgpu.scaled_ext_packed816 %v scale(%scale) blockSize(32) firstScaleLane(0) firstScaleByte(0) : vector<8xf8E5M2> to vector<8xf16>
// CHECK: amdgpu.scaled_ext_packed816
%ret1 = amdgpu.scaled_ext_packed816 %v scale(%scale) blockSize(32) firstScaleLane(0) firstScaleByte(0) : vector<8xf8E5M2> to vector<8xbf16>
// CHECK: amdgpu.scaled_ext_packed816
%ret2 = amdgpu.scaled_ext_packed816 %v scale(%scale) blockSize(32) firstScaleLane(0) firstScaleByte(0) : vector<8xf8E5M2> to vector<8xf32>
func.return %ret0, %ret1, %ret2 : vector<8xf16>, vector<8xbf16>, vector<8xf32>
}

// CHECK-LABEL: func.func @scaled_ext_packed816_fp6
func.func @scaled_ext_packed816_fp6(%v: vector<16xf6E2M3FN>, %scale: vector<4xf8E8M0FNU>) -> (vector<16xf16>, vector<16xbf16>, vector<16xf32>) {
// CHECK: amdgpu.scaled_ext_packed816
%ret0 = amdgpu.scaled_ext_packed816 %v scale(%scale) blockSize(32) firstScaleLane(0) firstScaleByte(0) : vector<16xf6E2M3FN> to vector<16xf16>
// CHECK: amdgpu.scaled_ext_packed816
%ret1 = amdgpu.scaled_ext_packed816 %v scale(%scale) blockSize(32) firstScaleLane(0) firstScaleByte(0) : vector<16xf6E2M3FN> to vector<16xbf16>
// CHECK: amdgpu.scaled_ext_packed816
%ret2 = amdgpu.scaled_ext_packed816 %v scale(%scale) blockSize(32) firstScaleLane(0) firstScaleByte(0) : vector<16xf6E2M3FN> to vector<16xf32>
func.return %ret0, %ret1, %ret2 : vector<16xf16>, vector<16xbf16>, vector<16xf32>
}

// CHECK-LABEL: func.func @scaled_ext_packed816_bf16
func.func @scaled_ext_packed816_bf16(%v: vector<16xf6E3M2FN>, %scale: vector<4xf8E8M0FNU>) -> (vector<16xf16>, vector<16xbf16>, vector<16xf32>) {
// CHECK: amdgpu.scaled_ext_packed816
%ret0 = amdgpu.scaled_ext_packed816 %v scale(%scale) blockSize(32) firstScaleLane(0) firstScaleByte(0) : vector<16xf6E3M2FN> to vector<16xf16>
// CHECK: amdgpu.scaled_ext_packed816
%ret1 = amdgpu.scaled_ext_packed816 %v scale(%scale) blockSize(32) firstScaleLane(0) firstScaleByte(0) : vector<16xf6E3M2FN> to vector<16xbf16>
// CHECK: amdgpu.scaled_ext_packed816
%ret2 = amdgpu.scaled_ext_packed816 %v scale(%scale) blockSize(32) firstScaleLane(0) firstScaleByte(0) : vector<16xf6E3M2FN> to vector<16xf32>
func.return %ret0, %ret1, %ret2 : vector<16xf16>, vector<16xbf16>, vector<16xf32>
}

// CHECK-LABEL: func.func @packed_scaled_trunc_f8e4m3_f32
// CHECK: amdgpu.packed_scaled_trunc
func.func @packed_scaled_trunc_f8e4m3_f32(%v: vector<2xf32>, %scale: f32) -> vector<4xf8E4M3FN> {
Expand Down