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[AMDGPU] Add regbankselect rules for G_ADD/SUB and variants #159860

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Merged
merged 3 commits into from
Oct 30, 2025
Merged

[AMDGPU] Add regbankselect rules for G_ADD/SUB and variants #159860

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fc1e872
[AMDGPU] Add regbankselect rules for G_ADD/SUB and variants
gandhi56 Sep 19, 2025
64bb037
Eliminate G_TRUNC to S1 SGPR
gandhi56 Oct 24, 2025
bd49109
Improve tests
gandhi56 Oct 29, 2025
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15 changes: 14 additions & 1 deletion llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -500,6 +500,16 @@ void RegBankLegalizeHelper::lowerUnpackMinMax(MachineInstr &MI) {
MI.eraseFromParent();
}

void RegBankLegalizeHelper::lowerUnpackAExt(MachineInstr &MI) {
auto [Op1Lo, Op1Hi] = unpackAExt(MI.getOperand(1).getReg());
auto [Op2Lo, Op2Hi] = unpackAExt(MI.getOperand(2).getReg());
auto ResLo = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {Op1Lo, Op2Lo});
auto ResHi = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {Op1Hi, Op2Hi});
B.buildBuildVectorTrunc(MI.getOperand(0).getReg(),
{ResLo.getReg(0), ResHi.getReg(0)});
MI.eraseFromParent();
}

static bool isSignedBFE(MachineInstr &MI) {
if (GIntrinsic *GI = dyn_cast<GIntrinsic>(&MI))
return (GI->is(Intrinsic::amdgcn_sbfe));
Expand Down Expand Up @@ -804,6 +814,8 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI,
}
break;
}
case UnpackAExt:
return lowerUnpackAExt(MI);
case WidenMMOToS32:
return widenMMOToS32(cast<GAnyLoad>(MI));
}
Expand Down Expand Up @@ -1120,7 +1132,8 @@ void RegBankLegalizeHelper::applyMappingDst(
assert(RB == SgprRB);
Register NewDst = MRI.createVirtualRegister(SgprRB_S32);
Op.setReg(NewDst);
B.buildTrunc(Reg, NewDst);
if (!MRI.use_empty(Reg))
B.buildTrunc(Reg, NewDst);
break;
}
case InvalidMapping: {
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
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Expand Up @@ -124,6 +124,7 @@ class RegBankLegalizeHelper {
void lowerSplitTo32Select(MachineInstr &MI);
void lowerSplitTo32SExtInReg(MachineInstr &MI);
void lowerUnpackMinMax(MachineInstr &MI);
void lowerUnpackAExt(MachineInstr &MI);
};

} // end namespace AMDGPU
Expand Down
14 changes: 13 additions & 1 deletion llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
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Expand Up @@ -470,7 +470,19 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(S16, {{Sgpr32Trunc}, {Sgpr32AExt, Sgpr32AExt}})
.Div(S16, {{Vgpr16}, {Vgpr16, Vgpr16}})
.Uni(S32, {{Sgpr32}, {Sgpr32, Sgpr32}})
.Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}});
.Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}})
.Uni(V2S16, {{SgprV2S16}, {SgprV2S16, SgprV2S16}, UnpackAExt})
.Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}})
.Uni(S64, {{Sgpr64}, {Sgpr64, Sgpr64}})
.Div(S64, {{Vgpr64}, {Vgpr64, Vgpr64}});

addRulesForGOpcs({G_UADDO, G_USUBO}, Standard)
.Uni(S32, {{Sgpr32, Sgpr32Trunc}, {Sgpr32, Sgpr32}})
.Div(S32, {{Vgpr32, Vcc}, {Vgpr32, Vgpr32}});

addRulesForGOpcs({G_UADDE, G_USUBE}, Standard)
.Uni(S32, {{Sgpr32, Sgpr32Trunc}, {Sgpr32, Sgpr32, Sgpr32AExtBoolInReg}})
.Div(S32, {{Vgpr32, Vcc}, {Vgpr32, Vgpr32, Vcc}});

addRulesForGOpcs({G_MUL}, Standard).Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}});

Expand Down
3 changes: 2 additions & 1 deletion llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
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Expand Up @@ -223,7 +223,8 @@ enum LoweringMethodID {
UniCstExt,
SplitLoad,
WidenLoad,
WidenMMOToS32
WidenMMOToS32,
UnpackAExt
};

enum FastRulesTypes {
Expand Down
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