AMDGPU: Remove wrapper around TRI::getRegClass #159885
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This was referenced Sep 19, 2025
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@llvm/pr-subscribers-llvm-globalisel @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) ChangesThis shadows the member in the base class, but differs slightly Full diff: https://github.com/llvm/llvm-project/pull/159885.diff 4 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 533c130364249..2710b98488e99 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -1301,10 +1301,11 @@ void SIFoldOperandsImpl::foldOperand(
continue;
const int SrcIdx = MovOp == AMDGPU::V_MOV_B16_t16_e64 ? 2 : 1;
- const TargetRegisterClass *MovSrcRC =
- TRI->getRegClass(TII->getOpRegClassID(MovDesc.operands()[SrcIdx]));
- if (MovSrcRC) {
+ int16_t RegClassID = TII->getOpRegClassID(MovDesc.operands()[SrcIdx]);
+ if (RegClassID != -1) {
+ const TargetRegisterClass *MovSrcRC = TRI->getRegClass(RegClassID);
+
if (UseSubReg)
MovSrcRC = TRI->getMatchingSuperRegClass(SrcRC, MovSrcRC, UseSubReg);
if (!MRI->constrainRegClass(SrcReg, MovSrcRC))
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 06190323dda8f..a368a0de891ea 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5964,7 +5964,7 @@ SIInstrInfo::getRegClass(const MCInstrDesc &TID, unsigned OpNum,
return nullptr;
const MCOperandInfo &OpInfo = TID.operands()[OpNum];
int16_t RegClass = getOpRegClassID(OpInfo);
- return RI.getRegClass(RegClass);
+ return RegClass < 0 ? nullptr : RI.getRegClass(RegClass);
}
const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
@@ -5982,7 +5982,8 @@ const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
return RI.getPhysRegBaseClass(Reg);
}
- return RI.getRegClass(getOpRegClassID(Desc.operands()[OpNo]));
+ int16_t RegClass = getOpRegClassID(Desc.operands()[OpNo]);
+ return RegClass < 0 ? nullptr : RI.getRegClass(RegClass);
}
void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index b019c98f15ee2..af7f0cbd4ae7a 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3897,17 +3897,6 @@ const TargetRegisterClass *SIRegisterInfo::getVGPR64Class() const {
: &AMDGPU::VReg_64RegClass;
}
-// FIXME: This should be deleted
-const TargetRegisterClass *
-SIRegisterInfo::getRegClass(unsigned RCID) const {
- switch ((int)RCID) {
- case -1:
- return nullptr;
- default:
- return AMDGPUGenRegisterInfo::getRegClass(RCID);
- }
-}
-
// Find reaching register definition
MachineInstr *SIRegisterInfo::findReachingDef(Register Reg, unsigned SubReg,
MachineInstr &Use,
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 7b91ba7bc581f..813f6bb1a503a 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -391,8 +391,6 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
MCRegister getExec() const;
- const TargetRegisterClass *getRegClass(unsigned RCID) const;
-
// Find reaching register definition
MachineInstr *findReachingDef(Register Reg, unsigned SubReg,
MachineInstr &Use,
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rampitec
approved these changes
Sep 22, 2025
This shadows the member in the base class, but differs slightly in behavior. The base method doesn't check for the invalid case.
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This shadows the member in the base class, but differs slightly
in behavior. The base method doesn't check for the invalid case.