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AMDGPU: Remove wrapper around TRI::getRegClass #159885

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AMDGPU: Remove wrapper around TRI::getRegClass #159885

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7 changes: 4 additions & 3 deletions llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1309,10 +1309,11 @@ void SIFoldOperandsImpl::foldOperand(
continue;

const int SrcIdx = MovOp == AMDGPU::V_MOV_B16_t16_e64 ? 2 : 1;
const TargetRegisterClass *MovSrcRC =
TRI->getRegClass(TII->getOpRegClassID(MovDesc.operands()[SrcIdx]));

if (MovSrcRC) {
int16_t RegClassID = TII->getOpRegClassID(MovDesc.operands()[SrcIdx]);
if (RegClassID != -1) {
const TargetRegisterClass *MovSrcRC = TRI->getRegClass(RegClassID);

if (UseSubReg)
MovSrcRC = TRI->getMatchingSuperRegClass(SrcRC, MovSrcRC, UseSubReg);

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5 changes: 3 additions & 2 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6041,7 +6041,7 @@ SIInstrInfo::getRegClass(const MCInstrDesc &TID, unsigned OpNum,
return nullptr;
const MCOperandInfo &OpInfo = TID.operands()[OpNum];
int16_t RegClass = getOpRegClassID(OpInfo);
return RI.getRegClass(RegClass);
return RegClass < 0 ? nullptr : RI.getRegClass(RegClass);
}

const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
Expand All @@ -6059,7 +6059,8 @@ const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
return RI.getPhysRegBaseClass(Reg);
}

return RI.getRegClass(getOpRegClassID(Desc.operands()[OpNo]));
int16_t RegClass = getOpRegClassID(Desc.operands()[OpNo]);
return RegClass < 0 ? nullptr : RI.getRegClass(RegClass);
}

void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {
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11 changes: 0 additions & 11 deletions llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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Expand Up @@ -3893,17 +3893,6 @@ const TargetRegisterClass *SIRegisterInfo::getVGPR64Class() const {
: &AMDGPU::VReg_64RegClass;
}

// FIXME: This should be deleted
const TargetRegisterClass *
SIRegisterInfo::getRegClass(unsigned RCID) const {
switch ((int)RCID) {
case -1:
return nullptr;
default:
return AMDGPUGenRegisterInfo::getRegClass(RCID);
}
}

// Find reaching register definition
MachineInstr *SIRegisterInfo::findReachingDef(Register Reg, unsigned SubReg,
MachineInstr &Use,
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2 changes: 0 additions & 2 deletions llvm/lib/Target/AMDGPU/SIRegisterInfo.h
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Expand Up @@ -391,8 +391,6 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {

MCRegister getExec() const;

const TargetRegisterClass *getRegClass(unsigned RCID) const;

// Find reaching register definition
MachineInstr *findReachingDef(Register Reg, unsigned SubReg,
MachineInstr &Use,
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