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[AArch64][SVE] Optimize logical ops with convert.to.svbool. #160408

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[AArch64][SVE] Optimize logical ops with convert.to.svbool. #160408

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[AArch64][SVE] Optimize logical ops with convert.to.svbool
miloserdow Sep 23, 2025
384109d
Merge branch 'main' into sve-intrinsic-add-or-with-all-true
miloserdow Oct 28, 2025
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40 changes: 37 additions & 3 deletions llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1469,8 +1469,17 @@ static SVEIntrinsicInfo constructSVEIntrinsicInfo(IntrinsicInst &II) {
return SVEIntrinsicInfo::defaultUndefOp().setMatchingIROpcode(
Instruction::UDiv);

case Intrinsic::aarch64_sve_addqv:
case Intrinsic::aarch64_sve_and_z:
return SVEIntrinsicInfo::defaultZeroingOp().setMatchingIROpcode(
Instruction::And);
case Intrinsic::aarch64_sve_orr_z:
return SVEIntrinsicInfo::defaultZeroingOp().setMatchingIROpcode(
Instruction::Or);
case Intrinsic::aarch64_sve_eor_z:
return SVEIntrinsicInfo::defaultZeroingOp().setMatchingIROpcode(
Instruction::Xor);

case Intrinsic::aarch64_sve_addqv:
case Intrinsic::aarch64_sve_bic_z:
case Intrinsic::aarch64_sve_brka_z:
case Intrinsic::aarch64_sve_brkb_z:
Expand All @@ -1479,13 +1488,11 @@ static SVEIntrinsicInfo constructSVEIntrinsicInfo(IntrinsicInst &II) {
case Intrinsic::aarch64_sve_brkpb_z:
case Intrinsic::aarch64_sve_cntp:
case Intrinsic::aarch64_sve_compact:
case Intrinsic::aarch64_sve_eor_z:
case Intrinsic::aarch64_sve_eorv:
case Intrinsic::aarch64_sve_eorqv:
case Intrinsic::aarch64_sve_nand_z:
case Intrinsic::aarch64_sve_nor_z:
case Intrinsic::aarch64_sve_orn_z:
case Intrinsic::aarch64_sve_orr_z:
case Intrinsic::aarch64_sve_orv:
case Intrinsic::aarch64_sve_orqv:
case Intrinsic::aarch64_sve_pnext:
Expand Down Expand Up @@ -1659,6 +1666,30 @@ simplifySVEIntrinsicBinOp(InstCombiner &IC, IntrinsicInst &II,
return ⅈ
}

// If both operands are convert.to.svbool from the same narrower type, try to
// simplify the operation at that narrower type first.
if (isAllActivePredicate(Pg)) {
auto *ConvIntr1 = dyn_cast<IntrinsicInst>(Op1);
auto *ConvIntr2 = dyn_cast<IntrinsicInst>(Op2);
if (ConvIntr1 && ConvIntr2 &&
ConvIntr1->getIntrinsicID() ==
Intrinsic::aarch64_sve_convert_to_svbool &&
ConvIntr2->getIntrinsicID() ==
Intrinsic::aarch64_sve_convert_to_svbool) {
Value *NarrowOp1 = ConvIntr1->getArgOperand(0);
Value *NarrowOp2 = ConvIntr2->getArgOperand(0);
Comment on lines +1672 to +1680
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@paulwalker-arm paulwalker-arm Nov 5, 2025 •
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Perhaps use PatternMatch, something like:

Value *NarrowOp1, *NarrowOp2;
if (match(Op1, m_Intrinsic<Intrinsic::aarch64_sve_convert_to_svbool>(m_Value(NarrowOp1))) &&
    match(Op2, m_Intrinsic<Intrinsic::aarch64_sve_convert_to_svbool>(m_Value(NarrowOp2))))

if (NarrowOp1->getType() == NarrowOp2->getType()) {
if (Value *SimplifiedNarrow =
simplifyBinOp(Opc, NarrowOp1, NarrowOp2, DL)) {
Value *NewConv = IC.Builder.CreateIntrinsic(
Intrinsic::aarch64_sve_convert_to_svbool,
{SimplifiedNarrow->getType()}, {SimplifiedNarrow});
return IC.replaceInstUsesWith(II, NewConv);
}
}
}
}

// Only active lanes matter when simplifying the operation.
Op1 = stripInactiveLanes(Op1, Pg);
Op2 = stripInactiveLanes(Op2, Pg);
Expand All @@ -1679,6 +1710,9 @@ simplifySVEIntrinsicBinOp(InstCombiner &IC, IntrinsicInst &II,
if (IInfo.inactiveLanesAreNotDefined())
return IC.replaceInstUsesWith(II, SimpleII);

if (!IInfo.inactiveLanesTakenFromOperand())
return std::nullopt;

Value *Inactive = II.getOperand(IInfo.getOperandIdxInactiveLanesTakenFrom());

// The intrinsic does nothing (e.g. sve.mul(pg, A, 1.0)).
Expand Down
123 changes: 123 additions & 0 deletions llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-and-or-with-all-true.ll
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@@ -0,0 +1,123 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --tool ../../llvm-build/bin/opt
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@paulwalker-arm paulwalker-arm Nov 5, 2025

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This will prevent others from regenerating the CHECK lines unless the path to their opt binary matches yours. I think you need to delete this NOTE and regenerate using --opt-binary instead of --tool.

; RUN: opt -passes=instcombine -mtriple aarch64 -mattr=+sve -S < %s | FileCheck %s
;
; Test AArch64-specific InstCombine optimizations for SVE logical operations
; with all-true predicates.
; - a AND true = a
; - a OR true = true

declare <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
declare <vscale x 16 x i1> @llvm.aarch64.sve.orr.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
declare <vscale x 16 x i1> @llvm.aarch64.sve.eor.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>)
declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>)
declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>)
declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>)
declare <vscale x 8 x i1> @llvm.aarch64.sve.pnext.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>)
Comment on lines +9 to +16
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@paulwalker-arm paulwalker-arm Nov 5, 2025

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We don't need to add these declarations anymore.


define <vscale x 16 x i1> @test_and_convert_all_true_right_b16(<vscale x 8 x i1> %x) {
; CHECK-LABEL: @test_and_convert_all_true_right_b16(
; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[X:%.*]])
; CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
;
%conv_x = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %x)
%conv_true = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> splat (i1 true))
%result = tail call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> splat (i1 true), <vscale x 16 x i1> %conv_x, <vscale x 16 x i1> %conv_true)
ret <vscale x 16 x i1> %result
}

define <vscale x 16 x i1> @test_and_convert_all_true_left_b16(<vscale x 8 x i1> %x) {
; CHECK-LABEL: @test_and_convert_all_true_left_b16(
; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[X:%.*]])
; CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
;
%conv_x = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %x)
%conv_true = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> splat (i1 true))
%result = tail call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> splat (i1 true), <vscale x 16 x i1> %conv_true, <vscale x 16 x i1> %conv_x)
ret <vscale x 16 x i1> %result
}

define <vscale x 16 x i1> @test_or_convert_all_true_right_b16(<vscale x 8 x i1> %x) {
; CHECK-LABEL: @test_or_convert_all_true_right_b16(
; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> splat (i1 true))
; CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
;
%conv_x = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %x)
%conv_true = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> splat (i1 true))
%result = tail call <vscale x 16 x i1> @llvm.aarch64.sve.orr.z.nxv16i1(<vscale x 16 x i1> splat (i1 true), <vscale x 16 x i1> %conv_x, <vscale x 16 x i1> %conv_true)
ret <vscale x 16 x i1> %result
}

define <vscale x 16 x i1> @test_or_convert_all_true_left_b16(<vscale x 8 x i1> %x) {
; CHECK-LABEL: @test_or_convert_all_true_left_b16(
; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> splat (i1 true))
; CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
;
%conv_x = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %x)
%conv_true = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> splat (i1 true))
%result = tail call <vscale x 16 x i1> @llvm.aarch64.sve.orr.z.nxv16i1(<vscale x 16 x i1> splat (i1 true), <vscale x 16 x i1> %conv_true, <vscale x 16 x i1> %conv_x)
ret <vscale x 16 x i1> %result
}
define <vscale x 16 x i1> @test_and_convert_all_true_b32(<vscale x 4 x i1> %x) {
; CHECK-LABEL: @test_and_convert_all_true_b32(
; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[X:%.*]])
; CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
;
%conv_x = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %x)
%conv_true = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> splat (i1 true))
%result = tail call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> splat (i1 true), <vscale x 16 x i1> %conv_x, <vscale x 16 x i1> %conv_true)
ret <vscale x 16 x i1> %result
}

define <vscale x 16 x i1> @test_and_convert_all_true_b64(<vscale x 2 x i1> %x) {
; CHECK-LABEL: @test_and_convert_all_true_b64(
; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[X:%.*]])
; CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
;
%conv_x = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %x)
%conv_true = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> splat (i1 true))
%result = tail call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> splat (i1 true), <vscale x 16 x i1> %conv_x, <vscale x 16 x i1> %conv_true)
ret <vscale x 16 x i1> %result
}

; Negative test
define <vscale x 16 x i1> @test_and_convert_different_granularities(<vscale x 8 x i1> %x, <vscale x 4 x i1> %y) {
; CHECK-LABEL: @test_and_convert_different_granularities(
; CHECK-NEXT: [[CONV_X:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[X:%.*]])
; CHECK-NEXT: [[CONV_Y:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[Y:%.*]])
; CHECK-NEXT: [[RESULT:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> splat (i1 true), <vscale x 16 x i1> [[CONV_X]], <vscale x 16 x i1> [[CONV_Y]])
; CHECK-NEXT: ret <vscale x 16 x i1> [[RESULT]]
;
%conv_x = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %x)
%conv_y = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %y)
%result = tail call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> splat (i1 true), <vscale x 16 x i1> %conv_x, <vscale x 16 x i1> %conv_y)
ret <vscale x 16 x i1> %result
}

; Negative test
define <vscale x 16 x i1> @test_and_convert_non_all_true_predicate(<vscale x 16 x i1> %pred, <vscale x 8 x i1> %x) {
; CHECK-LABEL: @test_and_convert_non_all_true_predicate(
; CHECK-NEXT: [[CONV_X:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[X:%.*]])
; CHECK-NEXT: [[CONV_TRUE:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> splat (i1 true))
; CHECK-NEXT: [[RESULT:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> [[PRED:%.*]], <vscale x 16 x i1> [[CONV_X]], <vscale x 16 x i1> [[CONV_TRUE]])
; CHECK-NEXT: ret <vscale x 16 x i1> [[RESULT]]
;
%conv_x = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %x)
%conv_true = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> splat (i1 true))
%result = tail call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> %pred, <vscale x 16 x i1> %conv_x, <vscale x 16 x i1> %conv_true)
ret <vscale x 16 x i1> %result
}

; Negative test
define <vscale x 16 x i1> @test_and_convert_no_all_true(<vscale x 8 x i1> %x, <vscale x 8 x i1> %y) {
; CHECK-LABEL: @test_and_convert_no_all_true(
; CHECK-NEXT: [[CONV_X:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[X:%.*]])
; CHECK-NEXT: [[CONV_Y:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[Y:%.*]])
; CHECK-NEXT: [[RESULT:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> splat (i1 true), <vscale x 16 x i1> [[CONV_X]], <vscale x 16 x i1> [[CONV_Y]])
; CHECK-NEXT: ret <vscale x 16 x i1> [[RESULT]]
;
%conv_x = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %x)
%conv_y = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %y)
%result = tail call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> splat (i1 true), <vscale x 16 x i1> %conv_x, <vscale x 16 x i1> %conv_y)
ret <vscale x 16 x i1> %result
}