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[LLVM][CodeGen] Check Non Saturate Case in isSaturatingMinMax #160637

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Merged
merged 3 commits into from
Oct 3, 2025
Merged

[LLVM][CodeGen] Check Non Saturate Case in isSaturatingMinMax #160637

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9b4a9c6
Fix Issue #160611
ningxinr Sep 25, 2025
f6db9a0
Addressed feedbacks and fixed typos
ningxinr Sep 29, 2025
baf5cde
Added the non sat comment
ningxinr Sep 29, 2025
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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6047,7 +6047,7 @@ static SDValue isSaturatingMinMax(SDValue N0, SDValue N1, SDValue N2,
}

if (MaxC == 0 && MinCPlus1.isPowerOf2()) {
BW = MinCPlus1.exactLogBase2();
BW = std::max(MinCPlus1.exactLogBase2(), 1);
Unsigned = true;
return N02;
}
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24 changes: 24 additions & 0 deletions llvm/test/CodeGen/AArch64/fpclamptosat.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1026,6 +1026,30 @@ entry:
ret i64 %conv6
}

define i32 @ustest_f16const_i32() {
; CHECK-CVT-LABEL: ustest_f16const_i32:
; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: mov w8, #2143289344 // =0x7fc00000
; CHECK-CVT-NEXT: fmov s0, w8
; CHECK-CVT-NEXT: fcvtzs w8, s0
; CHECK-CVT-NEXT: and w8, w8, w8, asr #31
; CHECK-CVT-NEXT: bic w0, w8, w8, asr #31
; CHECK-CVT-NEXT: ret
;
; CHECK-FP16-LABEL: ustest_f16const_i32:
; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: mov w8, #32256 // =0x7e00
; CHECK-FP16-NEXT: fmov h0, w8
; CHECK-FP16-NEXT: fcvtzs w8, h0
; CHECK-FP16-NEXT: and w8, w8, w8, asr #31
; CHECK-FP16-NEXT: bic w0, w8, w8, asr #31
; CHECK-FP16-NEXT: ret
%1 = fptosi half 0xH7E00 to i32
%2 = call i32 @llvm.smin.i32(i32 0, i32 %1)
%3 = call i32 @llvm.smax.i32(i32 %2, i32 0)
ret i32 %3
}

declare i32 @llvm.smin.i32(i32, i32)
declare i32 @llvm.smax.i32(i32, i32)
declare i32 @llvm.umin.i32(i32, i32)
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39 changes: 39 additions & 0 deletions llvm/test/CodeGen/RISCV/fpclamptosat.ll
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Expand Up @@ -3829,6 +3829,45 @@ entry:
ret i64 %conv6
}

define i32 @ustest_f16const_i32() {
; CHECK-LABEL: ustest_f16const_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: cvttss2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ecx
; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: sarl $31, %eax
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: andl %ecx, %eax
; CHECK-NEXT: cmovlel %edx, %eax
; CHECK-NEXT: retq
; RV32-LABEL: ustest_f16const_i32:
; RV32: # %bb.0:
; RV32-NEXT: lui a0, 523264
; RV32-NEXT: fmv.w.x fa5, a0
; RV32-NEXT: fcvt.w.s a0, fa5, rtz
; RV32-NEXT: srai a1, a0, 31
; RV32-NEXT: and a0, a1, a0
; RV32-NEXT: sgtz a1, a0
; RV32-NEXT: neg a1, a1
; RV32-NEXT: and a0, a1, a0
; RV32-NEXT: ret
;
; RV64-LABEL: ustest_f16const_i32:
; RV64: # %bb.0:
; RV64-NEXT: lui a0, 523264
; RV64-NEXT: fmv.w.x fa5, a0
; RV64-NEXT: fcvt.l.s a0, fa5, rtz
; RV64-NEXT: srai a1, a0, 63
; RV64-NEXT: and a0, a1, a0
; RV64-NEXT: sgtz a1, a0
; RV64-NEXT: neg a1, a1
; RV64-NEXT: and a0, a1, a0
; RV64-NEXT: ret
%1 = fptosi half 0xH7E00 to i32
%2 = call i32 @llvm.smin.i32(i32 0, i32 %1)
%3 = call i32 @llvm.smax.i32(i32 %2, i32 0)
ret i32 %3
}

declare i32 @llvm.smin.i32(i32, i32)
declare i32 @llvm.smax.i32(i32, i32)
declare i32 @llvm.umin.i32(i32, i32)
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16 changes: 16 additions & 0 deletions llvm/test/CodeGen/X86/fpclamptosat.ll
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Expand Up @@ -1170,6 +1170,22 @@ entry:
ret i64 %conv6
}

define i32 @ustest_f16const_i32() {
; CHECK-LABEL: ustest_f16const_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: cvttss2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ecx
; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: sarl $31, %eax
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: andl %ecx, %eax
; CHECK-NEXT: cmovlel %edx, %eax
; CHECK-NEXT: retq
%1 = fptosi half 0xH7E00 to i32
%2 = call i32 @llvm.smin.i32(i32 0, i32 %1)
%3 = call i32 @llvm.smax.i32(i32 %2, i32 0)
ret i32 %3
}

declare i32 @llvm.smin.i32(i32, i32)
declare i32 @llvm.smax.i32(i32, i32)
declare i32 @llvm.umin.i32(i32, i32)
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