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[AArch64][GlobalISel] SIMD fpcvt codegen for fptoi(_sat) #160831

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Merged
Lukacma merged 6 commits into from
Oct 24, 2025
Merged

[AArch64][GlobalISel] SIMD fpcvt codegen for fptoi(_sat) #160831

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76a5510
Add simd fpcvt codegen for fptoi(_sat)
Lukacma Sep 26, 2025
1a58bd5
Test fix
Lukacma Oct 3, 2025
3892261
remove unused patterns
Lukacma Oct 7, 2025
5dfb123
FIx missing feature guards
Lukacma Oct 17, 2025
cf8252b
Fix rounding tests to work with globalISel
Lukacma Oct 22, 2025
fe14bb8
Merge branch 'main' into cvt-fptosi
Lukacma Oct 24, 2025
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64InstrFormats.td
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Expand Up @@ -5302,7 +5302,7 @@ multiclass FPToIntegerUnscaled<bits<2> rmode, bits<3> opcode, string asm,
}

multiclass FPToIntegerSIMDScalar<bits<2> rmode, bits<3> opcode, string asm,
SDPatternOperator OpN = null_frag> {
SDPatternOperator OpN> {
// double-precision to 32-bit SIMD/FPR
def SDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, FPR32, asm,
[(set FPR32:$Rd, (i32 (OpN (f64 FPR64:$Rn))))]> {
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300 changes: 193 additions & 107 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.td
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18 changes: 14 additions & 4 deletions llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -852,19 +852,29 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
break;
}
case TargetOpcode::G_FPTOSI_SAT:
case TargetOpcode::G_FPTOUI_SAT: {
case TargetOpcode::G_FPTOUI_SAT:
case TargetOpcode::G_FPTOSI:
case TargetOpcode::G_FPTOUI: {
LLT DstType = MRI.getType(MI.getOperand(0).getReg());
if (DstType.isVector())
break;
if (DstType == LLT::scalar(16)) {
OpRegBankIdx = {PMI_FirstFPR, PMI_FirstFPR};
break;
}
OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR};
TypeSize DstSize = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
TypeSize SrcSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, TRI);
if (((DstSize == SrcSize) || STI.hasFeature(AArch64::FeatureFPRCVT)) &&
all_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
[&](const MachineInstr &UseMI) {
return onlyUsesFP(UseMI, MRI, TRI) ||
prefersFPUse(UseMI, MRI, TRI);
}))
OpRegBankIdx = {PMI_FirstFPR, PMI_FirstFPR};
else
OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR};
break;
}
case TargetOpcode::G_FPTOSI:
case TargetOpcode::G_FPTOUI:
case TargetOpcode::G_INTRINSIC_LRINT:
case TargetOpcode::G_INTRINSIC_LLRINT:
if (MRI.getType(MI.getOperand(0).getReg()).isVector())
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
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Expand Up @@ -96,7 +96,7 @@ body: |
; CHECK-NEXT: [[SITOFP:%[0-9]+]]:fpr(s32) = G_SITOFP [[COPY1]](s32)
; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr(s32) = COPY [[COPY2]](s32)
; CHECK-NEXT: [[SELECT:%[0-9]+]]:fpr(s32) = G_SELECT [[COPY2]](s32), [[COPY3]], [[SITOFP]]
; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:gpr(s32) = G_FPTOSI [[SELECT]](s32)
; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:fpr(s32) = G_FPTOSI [[SELECT]](s32)
%0:_(s32) = COPY $w0
%2:_(s32) = COPY $w1
%3:_(s32) = COPY $w2
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