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[ARM][SDAG] Half promote llvm.lrint nodes. #161088

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Merged
merged 4 commits into from
Oct 7, 2025
Merged

[ARM][SDAG] Half promote llvm.lrint nodes. #161088

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9c966f7
[ARM][SDAG] Half promote llvm.lrint nodes.
davemgreen Oct 2, 2025
c0a4160
Make the fp16 run line use +fp-armv8
davemgreen Oct 2, 2025
324898f
Add a fparmv8 run line
davemgreen Oct 3, 2025
199cf09
Also add llrint, whilst I am here
davemgreen Oct 4, 2025
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7 changes: 5 additions & 2 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3740,7 +3740,10 @@ bool DAGTypeLegalizer::SoftPromoteHalfOperand(SDNode *N, unsigned OpNo) {
case ISD::STRICT_FP_TO_SINT:
case ISD::STRICT_FP_TO_UINT:
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT: Res = SoftPromoteHalfOp_FP_TO_XINT(N); break;
case ISD::FP_TO_UINT:
case ISD::LRINT:
Res = SoftPromoteHalfOp_Op0WithStrict(N);
break;
case ISD::FP_TO_SINT_SAT:
case ISD::FP_TO_UINT_SAT:
Res = SoftPromoteHalfOp_FP_TO_XINT_SAT(N); break;
Expand Down Expand Up @@ -3819,7 +3822,7 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfOp_FP_EXTEND(SDNode *N) {
return DAG.getNode(GetPromotionOpcode(SVT, RVT), SDLoc(N), RVT, Op);
}

SDValue DAGTypeLegalizer::SoftPromoteHalfOp_FP_TO_XINT(SDNode *N) {
SDValue DAGTypeLegalizer::SoftPromoteHalfOp_Op0WithStrict(SDNode *N) {
EVT RVT = N->getValueType(0);
bool IsStrict = N->isStrictFPOpcode();
SDValue Op = N->getOperand(IsStrict ? 1 : 0);
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
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Expand Up @@ -843,7 +843,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue SoftPromoteHalfOp_FAKE_USE(SDNode *N, unsigned OpNo);
SDValue SoftPromoteHalfOp_FCOPYSIGN(SDNode *N, unsigned OpNo);
SDValue SoftPromoteHalfOp_FP_EXTEND(SDNode *N);
SDValue SoftPromoteHalfOp_FP_TO_XINT(SDNode *N);
SDValue SoftPromoteHalfOp_Op0WithStrict(SDNode *N);
SDValue SoftPromoteHalfOp_FP_TO_XINT_SAT(SDNode *N);
SDValue SoftPromoteHalfOp_SETCC(SDNode *N);
SDValue SoftPromoteHalfOp_SELECT_CC(SDNode *N, unsigned OpNo);
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/ARM/ARMISelLowering.cpp
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Expand Up @@ -1353,6 +1353,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
setOperationAction(ISD::FLOG, MVT::f16, Promote);
setOperationAction(ISD::FLOG10, MVT::f16, Promote);
setOperationAction(ISD::FLOG2, MVT::f16, Promote);
setOperationAction(ISD::LRINT, MVT::f16, Expand);

setOperationAction(ISD::FROUND, MVT::f16, Legal);
setOperationAction(ISD::FROUNDEVEN, MVT::f16, Legal);
Expand Down
48 changes: 36 additions & 12 deletions llvm/test/CodeGen/ARM/lrint-conv.ll
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@@ -1,14 +1,43 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=armv7-none-eabi -float-abi=soft | FileCheck %s --check-prefixes=CHECK,CHECK-SOFT
; RUN: llc < %s -mtriple=armv7-none-eabihf -mattr=+vfp2 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16
; RUN: llc < %s -mtriple=armv7-none-eabihf -mattr=+vfp2,+fullfp16 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
; RUN: llc < %s -mtriple=armv8-none-eabihf -mattr=+fp-armv8 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FPv8
; RUN: llc < %s -mtriple=armv8-none-eabihf -mattr=+fp-armv8,+fullfp16 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FP16

; FIXME: crash
; define i32 @testmswh_builtin(half %x) {
; entry:
; %0 = tail call i32 @llvm.lrint.i32.f16(half %x)
; ret i32 %0
; }
define i32 @testmswh_builtin(half %x) {
; CHECK-SOFT-LABEL: testmswh_builtin:
; CHECK-SOFT: @ %bb.0: @ %entry
; CHECK-SOFT-NEXT: .save {r11, lr}
; CHECK-SOFT-NEXT: push {r11, lr}
; CHECK-SOFT-NEXT: bl __aeabi_h2f
; CHECK-SOFT-NEXT: pop {r11, lr}
; CHECK-SOFT-NEXT: b lrintf
;
; CHECK-NOFP16-LABEL: testmswh_builtin:
; CHECK-NOFP16: @ %bb.0: @ %entry
; CHECK-NOFP16-NEXT: .save {r11, lr}
; CHECK-NOFP16-NEXT: push {r11, lr}
; CHECK-NOFP16-NEXT: vmov r0, s0
; CHECK-NOFP16-NEXT: bl __aeabi_h2f
; CHECK-NOFP16-NEXT: vmov s0, r0
; CHECK-NOFP16-NEXT: pop {r11, lr}
; CHECK-NOFP16-NEXT: b lrintf
;
; CHECK-FPv8-LABEL: testmswh_builtin:
; CHECK-FPv8: @ %bb.0: @ %entry
; CHECK-FPv8-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-FPv8-NEXT: b lrintf
;
; CHECK-FP16-LABEL: testmswh_builtin:
; CHECK-FP16: @ %bb.0: @ %entry
; CHECK-FP16-NEXT: vrintx.f16 s0, s0
; CHECK-FP16-NEXT: vcvt.s32.f16 s0, s0
; CHECK-FP16-NEXT: vmov r0, s0
; CHECK-FP16-NEXT: bx lr
entry:
%0 = tail call i32 @llvm.lrint.i32.f16(half %x)
ret i32 %0
}

define i32 @testmsws_builtin(float %x) {
; CHECK-LABEL: testmsws_builtin:
Expand Down Expand Up @@ -39,8 +68,3 @@ entry:
%0 = tail call i32 @llvm.lrint.i32.f128(fp128 %x)
ret i32 %0
}

;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK-FP16: {{.*}}
; CHECK-NOFP16: {{.*}}
; CHECK-SOFT: {{.*}}
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