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[AArch64][GlobalISel] Legalize s16 G_FCONSTANT to avoid widening to G_CONSTANT #161205

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Merged
merged 4 commits into from
Oct 8, 2025
Merged

[AArch64][GlobalISel] Legalize s16 G_FCONSTANT to avoid widening to G_CONSTANT #161205

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d3ea33e
[AArch64][GlobalISel] Legalize s16 G_FCONSTANT to avoid widening to G…
HolyMolyCowMan Sep 29, 2025
cd6518d
Update tests
HolyMolyCowMan Sep 29, 2025
47a98ff
Convert s16 G_FCONSTANT to G_CONSTANT when better represented
HolyMolyCowMan Oct 3, 2025
3058b44
Move matchFConstantToConstant to post legalizer lowering
HolyMolyCowMan Oct 3, 2025
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4 changes: 2 additions & 2 deletions llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
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Expand Up @@ -678,8 +678,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.widenScalarToNextPow2(0)
.clampScalar(0, s8, s64);
getActionDefinitionsBuilder(G_FCONSTANT)
.legalFor({s32, s64, s128})
.legalFor(HasFP16, {s16})
// Always legalize s16 to prevent G_FCONSTANT being widened to G_CONSTANT
.legalFor({s16, s32, s64, s128})
.clampScalar(0, MinFPScalar, s128);

// FIXME: fix moreElementsToNextPow2
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5 changes: 3 additions & 2 deletions llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
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Expand Up @@ -48,8 +48,9 @@ body: |
; CHECK-NEXT: $w0 = COPY [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
; CHECK-NEXT: $x0 = COPY [[C1]](s64)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: $w0 = COPY [[C2]](s32)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C2]](s16)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
%0:_(s32) = G_FCONSTANT float 1.0
$w0 = COPY %0
%1:_(s64) = G_FCONSTANT double 2.0
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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp16-fconstant.mir
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Expand Up @@ -8,7 +8,7 @@ tracksRegLiveness: true
body: |
bb.0:
; NO-FP16-LABEL: name: fp16
; NO-FP16: %cst:_(s16) = G_CONSTANT i16 0
; NO-FP16: %cst:_(s16) = G_FCONSTANT half 0xH0000
; NO-FP16-NEXT: $h0 = COPY %cst(s16)
; NO-FP16-NEXT: RET_ReallyLR implicit $h0
;
Expand All @@ -26,7 +26,7 @@ tracksRegLiveness: true
body: |
bb.0:
; NO-FP16-LABEL: name: fp16_non_zero
; NO-FP16: %cst:_(s16) = G_CONSTANT i16 16384
; NO-FP16: %cst:_(s16) = G_FCONSTANT half 0xH4000
; NO-FP16-NEXT: $h0 = COPY %cst(s16)
; NO-FP16-NEXT: RET_ReallyLR implicit $h0
;
Expand All @@ -44,7 +44,7 @@ tracksRegLiveness: true
body: |
bb.1.entry:
; NO-FP16-LABEL: name: nan
; NO-FP16: %cst:_(s16) = G_CONSTANT i16 31745
; NO-FP16: %cst:_(s16) = G_FCONSTANT half 0xH7C01
; NO-FP16-NEXT: %ext:_(s32) = G_FPEXT %cst(s16)
; NO-FP16-NEXT: $w0 = COPY %ext(s32)
; NO-FP16-NEXT: RET_ReallyLR implicit $w0
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13 changes: 6 additions & 7 deletions llvm/test/CodeGen/AArch64/arm64-indexed-memory.ll
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Expand Up @@ -739,15 +739,14 @@ define ptr @postidx32_shalf(ptr %src, ptr %out, half %a) {
;
; GISEL-LABEL: postidx32_shalf:
; GISEL: ; %bb.0:
; GISEL-NEXT: mov w8, #0 ; =0x0
; GISEL-NEXT: ldr h1, [x0], #4
; GISEL-NEXT: fmov s2, w8
; GISEL-NEXT: movi d1, #0000000000000000
; GISEL-NEXT: ldr h2, [x0], #4
; GISEL-NEXT: ; kill: def $h0 killed $h0 def $s0
; GISEL-NEXT: fmov w9, s0
; GISEL-NEXT: fcvt s3, h1
; GISEL-NEXT: fmov w8, s1
; GISEL-NEXT: fcvt s2, h2
; GISEL-NEXT: fcmp s3, s2
; GISEL-NEXT: fcvt s3, h2
; GISEL-NEXT: fmov w8, s2
; GISEL-NEXT: fcvt s1, h1
; GISEL-NEXT: fcmp s3, s1
; GISEL-NEXT: csel w8, w8, w9, mi
; GISEL-NEXT: strh w8, [x1]
; GISEL-NEXT: ret
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30 changes: 20 additions & 10 deletions llvm/test/CodeGen/AArch64/dup.ll
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Expand Up @@ -1469,8 +1469,9 @@ define <2 x half> @loaddup_str_v2half(ptr %p) {
; CHECK-GI-LABEL: loaddup_str_v2half:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: ldr h0, [x0]
; CHECK-GI-NEXT: strh wzr, [x0]
; CHECK-GI-NEXT: movi d1, #0000000000000000
; CHECK-GI-NEXT: dup v0.4h, v0.h[0]
; CHECK-GI-NEXT: str h1, [x0]
; CHECK-GI-NEXT: ret
entry:
%a = load half, ptr %p
Expand Down Expand Up @@ -1526,8 +1527,9 @@ define <3 x half> @loaddup_str_v3half(ptr %p) {
; CHECK-GI-LABEL: loaddup_str_v3half:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: ldr h0, [x0]
; CHECK-GI-NEXT: strh wzr, [x0]
; CHECK-GI-NEXT: movi d1, #0000000000000000
; CHECK-GI-NEXT: dup v0.4h, v0.h[0]
; CHECK-GI-NEXT: str h1, [x0]
; CHECK-GI-NEXT: ret
entry:
%a = load half, ptr %p
Expand Down Expand Up @@ -1583,8 +1585,9 @@ define <4 x half> @loaddup_str_v4half(ptr %p) {
; CHECK-GI-LABEL: loaddup_str_v4half:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: ldr h0, [x0]
; CHECK-GI-NEXT: strh wzr, [x0]
; CHECK-GI-NEXT: movi d1, #0000000000000000
; CHECK-GI-NEXT: dup v0.4h, v0.h[0]
; CHECK-GI-NEXT: str h1, [x0]
; CHECK-GI-NEXT: ret
entry:
%a = load half, ptr %p
Expand Down Expand Up @@ -1639,8 +1642,9 @@ define <8 x half> @loaddup_str_v8half(ptr %p) {
; CHECK-GI-LABEL: loaddup_str_v8half:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: ldr h0, [x0]
; CHECK-GI-NEXT: strh wzr, [x0]
; CHECK-GI-NEXT: movi d1, #0000000000000000
; CHECK-GI-NEXT: dup v0.8h, v0.h[0]
; CHECK-GI-NEXT: str h1, [x0]
; CHECK-GI-NEXT: ret
entry:
%a = load half, ptr %p
Expand Down Expand Up @@ -1713,9 +1717,10 @@ define <16 x half> @loaddup_str_v16half(ptr %p) {
; CHECK-GI-LABEL: loaddup_str_v16half:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: ldr h1, [x0]
; CHECK-GI-NEXT: strh wzr, [x0]
; CHECK-GI-NEXT: movi d2, #0000000000000000
; CHECK-GI-NEXT: dup v0.8h, v1.h[0]
; CHECK-GI-NEXT: dup v1.8h, v1.h[0]
; CHECK-GI-NEXT: str h2, [x0]
; CHECK-GI-NEXT: ret
entry:
%a = load half, ptr %p
Expand Down Expand Up @@ -1771,8 +1776,9 @@ define <2 x bfloat> @loaddup_str_v2bfloat(ptr %p) {
; CHECK-GI-LABEL: loaddup_str_v2bfloat:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: ldr h0, [x0]
; CHECK-GI-NEXT: strh wzr, [x0]
; CHECK-GI-NEXT: movi d1, #0000000000000000
; CHECK-GI-NEXT: dup v0.4h, v0.h[0]
; CHECK-GI-NEXT: str h1, [x0]
; CHECK-GI-NEXT: ret
entry:
%a = load bfloat, ptr %p
Expand Down Expand Up @@ -1828,8 +1834,9 @@ define <3 x bfloat> @loaddup_str_v3bfloat(ptr %p) {
; CHECK-GI-LABEL: loaddup_str_v3bfloat:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: ldr h0, [x0]
; CHECK-GI-NEXT: strh wzr, [x0]
; CHECK-GI-NEXT: movi d1, #0000000000000000
; CHECK-GI-NEXT: dup v0.4h, v0.h[0]
; CHECK-GI-NEXT: str h1, [x0]
; CHECK-GI-NEXT: ret
entry:
%a = load bfloat, ptr %p
Expand Down Expand Up @@ -1885,8 +1892,9 @@ define <4 x bfloat> @loaddup_str_v4bfloat(ptr %p) {
; CHECK-GI-LABEL: loaddup_str_v4bfloat:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: ldr h0, [x0]
; CHECK-GI-NEXT: strh wzr, [x0]
; CHECK-GI-NEXT: movi d1, #0000000000000000
; CHECK-GI-NEXT: dup v0.4h, v0.h[0]
; CHECK-GI-NEXT: str h1, [x0]
; CHECK-GI-NEXT: ret
entry:
%a = load bfloat, ptr %p
Expand Down Expand Up @@ -1941,8 +1949,9 @@ define <8 x bfloat> @loaddup_str_v8bfloat(ptr %p) {
; CHECK-GI-LABEL: loaddup_str_v8bfloat:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: ldr h0, [x0]
; CHECK-GI-NEXT: strh wzr, [x0]
; CHECK-GI-NEXT: movi d1, #0000000000000000
; CHECK-GI-NEXT: dup v0.8h, v0.h[0]
; CHECK-GI-NEXT: str h1, [x0]
; CHECK-GI-NEXT: ret
entry:
%a = load bfloat, ptr %p
Expand Down Expand Up @@ -2015,9 +2024,10 @@ define <16 x bfloat> @loaddup_str_v16bfloat(ptr %p) {
; CHECK-GI-LABEL: loaddup_str_v16bfloat:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: ldr h1, [x0]
; CHECK-GI-NEXT: strh wzr, [x0]
; CHECK-GI-NEXT: movi d2, #0000000000000000
; CHECK-GI-NEXT: dup v0.8h, v1.h[0]
; CHECK-GI-NEXT: dup v1.8h, v1.h[0]
; CHECK-GI-NEXT: str h2, [x0]
; CHECK-GI-NEXT: ret
entry:
%a = load bfloat, ptr %p
Expand Down
21 changes: 11 additions & 10 deletions llvm/test/CodeGen/AArch64/f16-instructions.ll
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Expand Up @@ -782,18 +782,19 @@ define void @test_fccmp(half %in, ptr %out) {
;
; CHECK-CVT-GI-LABEL: test_fccmp:
; CHECK-CVT-GI: // %bb.0:
; CHECK-CVT-GI-NEXT: mov w8, #17664 // =0x4500
; CHECK-CVT-GI-NEXT: mov w9, #18432 // =0x4800
; CHECK-CVT-GI-NEXT: adrp x8, .LCPI29_0
; CHECK-CVT-GI-NEXT: // kill: def $h0 killed $h0 def $s0
; CHECK-CVT-GI-NEXT: fcvt s2, h0
; CHECK-CVT-GI-NEXT: fmov s1, w8
; CHECK-CVT-GI-NEXT: fmov s3, w9
; CHECK-CVT-GI-NEXT: fmov w9, s0
; CHECK-CVT-GI-NEXT: fcvt s1, h1
; CHECK-CVT-GI-NEXT: fcvt s3, h3
; CHECK-CVT-GI-NEXT: fcmp s2, s1
; CHECK-CVT-GI-NEXT: fccmp s2, s3, #4, mi
; CHECK-CVT-GI-NEXT: csel w8, w9, w8, gt
; CHECK-CVT-GI-NEXT: ldr h1, [x8, :lo12:.LCPI29_0]
; CHECK-CVT-GI-NEXT: adrp x8, .LCPI29_1
; CHECK-CVT-GI-NEXT: ldr h4, [x8, :lo12:.LCPI29_1]
; CHECK-CVT-GI-NEXT: fmov w8, s0
; CHECK-CVT-GI-NEXT: fcvt s3, h1
; CHECK-CVT-GI-NEXT: fmov w9, s1
; CHECK-CVT-GI-NEXT: fcvt s4, h4
; CHECK-CVT-GI-NEXT: fcmp s2, s3
; CHECK-CVT-GI-NEXT: fccmp s2, s4, #4, mi
; CHECK-CVT-GI-NEXT: csel w8, w8, w9, gt
; CHECK-CVT-GI-NEXT: strh w8, [x0]
; CHECK-CVT-GI-NEXT: ret
;
Expand Down
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