Skip to content

[PowerPC] Implement paddis #161572

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 3 commits into
base: main
Choose a base branch
from
Open

[PowerPC] Implement paddis #161572

Show file tree
Hide file tree
Changes from 2 commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
9d1457e
[PowerPC] Implement paddis
lei137 Sep 30, 2025
a3708ff
add LE encoding test
lei137 Oct 31, 2025
c8310e2
apply clang format suggestion
lei137 Oct 31, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 4 additions & 0 deletions llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -365,6 +365,10 @@ struct PPCOperand : public MCParsedAsmOperand {
bool isS16ImmX4() const { return isExtImm<16>(/*Signed*/ true, 4); }
bool isS16ImmX16() const { return isExtImm<16>(/*Signed*/ true, 16); }
bool isS17Imm() const { return isExtImm<17>(/*Signed*/ true, 1); }
bool isS32Imm() const {
// TODO: Is ContextImmediate needed?
return Kind == Expression || isSImm<32>();
}
bool isS34Imm() const {
// Once the PC-Rel ABI is finalized, evaluate whether a 34-bit
// ContextImmediate is needed.
Expand Down
9 changes: 9 additions & 0 deletions llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -47,6 +47,9 @@ static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
case PPC::fixup_ppc_half16ds:
case PPC::fixup_ppc_half16dq:
return Value & 0xfffc;
case PPC::fixup_ppc_pcrel32:
case PPC::fixup_ppc_imm32:
return Value & 0xffffffff;
case PPC::fixup_ppc_pcrel34:
case PPC::fixup_ppc_imm34:
return Value & 0x3ffffffff;
Expand All @@ -71,6 +74,8 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
case PPC::fixup_ppc_br24abs:
case PPC::fixup_ppc_br24_notoc:
return 4;
case PPC::fixup_ppc_pcrel32:
case PPC::fixup_ppc_imm32:
case PPC::fixup_ppc_pcrel34:
case PPC::fixup_ppc_imm34:
case FK_Data_8:
Expand Down Expand Up @@ -154,6 +159,8 @@ MCFixupKindInfo PPCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
{"fixup_ppc_brcond14abs", 16, 14, 0},
{"fixup_ppc_half16", 0, 16, 0},
{"fixup_ppc_half16ds", 0, 14, 0},
{"fixup_ppc_pcrel32", 0, 32, 0},
{"fixup_ppc_imm32", 0, 32, 0},
{"fixup_ppc_pcrel34", 0, 34, 0},
{"fixup_ppc_imm34", 0, 34, 0},
{"fixup_ppc_nofixup", 0, 0, 0}};
Expand All @@ -166,6 +173,8 @@ MCFixupKindInfo PPCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
{"fixup_ppc_brcond14abs", 2, 14, 0},
{"fixup_ppc_half16", 0, 16, 0},
{"fixup_ppc_half16ds", 2, 14, 0},
{"fixup_ppc_pcrel32", 0, 32, 0},
{"fixup_ppc_imm32", 0, 32, 0},
{"fixup_ppc_pcrel34", 0, 34, 0},
{"fixup_ppc_imm34", 0, 34, 0},
{"fixup_ppc_nofixup", 0, 0, 0}};
Expand Down
6 changes: 6 additions & 0 deletions llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -40,6 +40,12 @@ enum Fixups {
/// instrs like 'std'.
fixup_ppc_half16ds,

// A 32-bit fixup corresponding to PC-relative paddis.
fixup_ppc_pcrel32,

// A 32-bit fixup corresponding to Non-PC-relative paddis.
fixup_ppc_imm32,

// A 34-bit fixup corresponding to PC-relative paddi.
fixup_ppc_pcrel34,

Expand Down
12 changes: 12 additions & 0 deletions llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -430,6 +430,18 @@ void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
printOperand(MI, OpNo, STI, O);
}

void PPCInstPrinter::printS32ImmOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
if (MI->getOperand(OpNo).isImm()) {
long long Value = MI->getOperand(OpNo).getImm();
assert(isInt<32>(Value) && "Invalid s32imm argument!");
O << (long long)Value;
}
else
printOperand(MI, OpNo, STI, O);
}

void PPCInstPrinter::printS34ImmOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -80,6 +80,8 @@ class PPCInstPrinter : public MCInstPrinter {
const MCSubtargetInfo &STI, raw_ostream &O);
void printS16ImmOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printS32ImmOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printS34ImmOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printU16ImmOperand(const MCInst *MI, unsigned OpNo,
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -46,6 +46,7 @@ static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset,
case PPC::fixup_ppc_br24_notoc:
case PPC::fixup_ppc_brcond14:
case PPC::fixup_ppc_pcrel34:
case PPC::fixup_ppc_pcrel32:
PCRel = true;
}
Fixups.push_back(MCFixup::create(Offset, Value, Kind, PCRel));
Expand Down
44 changes: 44 additions & 0 deletions llvm/lib/Target/PowerPC/PPCInstrFuture.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -312,9 +312,41 @@ class 8RR_XX4Form_XTABC6_P<bits<6> opcode, dag OOL, dag IOL, string asmstr,
let Inst{63} = XT{5};
}

class MLS_DForm_R_SI32_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: PI<1, opcode, OOL, IOL, asmstr, itin> {
bits<5> RT;
bits<5> RA;
bits<32> SI;

let Pattern = pattern;

// The prefix.
let Inst{6...7} = 2;
let Inst{8} = 0;
let Inst{11} = PCRel;
let Inst{16...31} = SI{31...16};

// The instruction.
let Inst{38...42} = RT;
let Inst{43...47} = RA;
let Inst{48...63} = SI{15...0};
}

multiclass MLS_DForm_R_SI32_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
dag PCRel_IOL, string asmstr,
InstrItinClass itin> {
def NAME : MLS_DForm_R_SI32_RTA5<opcode, OOL, IOL, !strconcat(asmstr, ", 0"),
itin, []>;
def pc : MLS_DForm_R_SI32_RTA5<opcode, OOL, PCRel_IOL,
!strconcat(asmstr, ", 1"), itin, []>,
isPCRel;
}

//-------------------------- Instruction definitions -------------------------//
// Predicate combinations available:
// [IsISAFuture]
// [IsISAFuture, PrefixInstrs]
// [HasVSX, IsISAFuture]
// [HasVSX, PrefixInstrs, IsISAFuture]

Expand Down Expand Up @@ -346,6 +378,18 @@ let Predicates = [IsISAFuture] in {
}
}

let Predicates = [IsISAFuture, PrefixInstrs] in {
defm PADDIS : MLS_DForm_R_SI32_RTA5_p<15, (outs gprc:$RT),
(ins gprc_nor0:$RA, s32imm:$SI),
(ins immZero:$RA, s32imm_pcrel:$SI),
"paddis $RT, $RA, $SI", IIC_LdStLFD>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in
defm PADDIS8 : MLS_DForm_R_SI32_RTA5_p<15, (outs g8rc:$RT),
(ins g8rc_nox0:$RA, s32imm:$SI),
(ins immZero:$RA, s32imm_pcrel:$SI),
"paddis $RT, $RA, $SI", IIC_LdStLFD>;
}

let Predicates = [HasVSX, IsISAFuture] in {
let mayLoad = 1 in {
def LXVRL : XX1Form_memOp<31, 525, (outs vsrc:$XT),
Expand Down
19 changes: 19 additions & 0 deletions llvm/lib/Target/PowerPC/PPCRegisterInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -808,6 +808,25 @@ def s17imm64 : Operand<i64> {
let DecoderMethod = "decodeSImmOperand<16>";
let OperandType = "OPERAND_IMMEDIATE";
}
def PPCS32ImmAsmOperand : AsmOperandClass {
let Name = "S32Imm";
let PredicateMethod = "isS32Imm";
let RenderMethod = "addImmOperands";
}
def s32imm : Operand<i64> {
let PrintMethod = "printS32ImmOperand";
let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_imm32>";
let ParserMatchClass = PPCS32ImmAsmOperand;
let DecoderMethod = "decodeSImmOperand<32>";
let OperandType = "OPERAND_IMMEDIATE";
}
def s32imm_pcrel : Operand<i64> {
let PrintMethod = "printS32ImmOperand";
let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_pcrel32>";
let ParserMatchClass = PPCS32ImmAsmOperand;
let DecoderMethod = "decodeSImmOperand<32>";
let OperandType = "OPERAND_IMMEDIATE";
}
def PPCS34ImmAsmOperand : AsmOperandClass {
let Name = "S34Imm";
let PredicateMethod = "isS34Imm";
Expand Down
6 changes: 6 additions & 0 deletions llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -289,6 +289,12 @@
#CHECK: mtlpl 3, 4
0x7c,0x80,0x1a,0x26

#CHECK: paddis 10, 12, 1000000000, 0
0x06,0x00,0x3b,0x9a,0x3d,0x4c,0xca,0x00

#CHECK: paddis 10, 0, 1000000000, 1
0x06,0x10,0x3b,0x9a,0x3d,0x40,0xca,0x00

#CHECK: xxmulmul 8, 3, 4, 2
0xed,0x03,0x22,0x08

Expand Down
6 changes: 6 additions & 0 deletions llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -283,6 +283,12 @@
#CHECK: mtlpl 3, 4
0x26,0x1a,0x80,0x7c

#CHECK: paddis 10, 12, 1000000000, 0
0x9a,0x3b,0x00,0x06,0x00,0xca,0x4c,0x3d

#CHECK: paddis 10, 0, 1000000000, 1
0x9a,0x3b,0x10,0x06,0x00,0xca,0x40,0x3d

#CHECK: xxmulmul 8, 3, 4, 2
0x08,0x22,0x03,0xed

Expand Down
12 changes: 12 additions & 0 deletions llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -407,6 +407,18 @@
#CHECK-BE: mtlpl 3, 4 # encoding: [0x7c,0x80,0x1a,0x26]
#CHECK-LE: mtlpl 3, 4 # encoding: [0x26,0x1a,0x80,0x7c]

paddis 10, 12, 1000000000, 0
#CHECK-BE: paddis 10, 12, 1000000000, 0 # encoding: [0x06,0x00,0x3b,0x9a,
#CHECK-BE-SAME: 0x3d,0x4c,0xca,0x00]
#CHECK-LE: paddis 10, 12, 1000000000, 0 # encoding: [0x9a,0x3b,0x00,0x06,
#CHECK-LE-SAME: 0x00,0xca,0x4c,0x3d]

paddis 10, 0, 1000000000, 1
#CHECK-BE: paddis 10, 0, 1000000000, 1 # encoding: [0x06,0x10,0x3b,0x9a,
#CHECK-BE-SAME: 0x3d,0x40,0xca,0x00]
#CHECK-LE: paddis 10, 0, 1000000000, 1 # encoding: [0x9a,0x3b,0x10,0x06,
#CHECK-LE-SAME: 0x00,0xca,0x40,0x3d]

xxmulmul 8, 3, 4, 2
#CHECK-BE: xxmulmul 8, 3, 4, 2 # encoding: [0xed,0x03,0x22,0x08]
#CHECK-LE: xxmulmul 8, 3, 4, 2 # encoding: [0x08,0x22,0x03,0xed]
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/MC/PowerPC/ppc64-encoding-ISA31-errors.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -7,10 +7,10 @@
paddi 1, 1, 32, 1

# CHECK: error: invalid operand for instruction
pld 1, 32(1), 1
paddis 10, 5, 1000000000, 1

# CHECK: error: invalid operand for instruction
paddi 1, 1, 32, 1
Copy link
Contributor Author

@lei137 lei137 Oct 31, 2025 •
edited
Loading

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Removing since this is a duplicate of line 7.

pld 1, 32(1), 1

# CHECK: error: invalid operand for instruction
plbz 1, 32(1), 1
Expand Down
Loading