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[AMDGPU] Use correct SlotIndex to calculate live-out register set. #161720

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Merged
merged 3 commits into from
Oct 10, 2025
Merged

[AMDGPU] Use correct SlotIndex to calculate live-out register set. #161720

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d27a6de
[AMDGPU] Use correct SlotIndex to calculate live-out register set.
vpykhtin Oct 2, 2025
4874306
Use getMBBEndIdx(MBB).getPrevSlot() as getMBBLastIdx result.
vpykhtin Oct 3, 2025
9bf2639
Remove unrelated changes, use MBBLastSlot for live-throughs as well.
vpykhtin Oct 3, 2025
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15 changes: 13 additions & 2 deletions llvm/include/llvm/CodeGen/SlotIndexes.h
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Original file line number Diff line number Diff line change
Expand Up @@ -467,16 +467,27 @@ class raw_ostream;
return getMBBRange(mbb).first;
}

/// Returns the last index in the given basic block number.
/// Returns the index past the last valid index in the given basic block.
SlotIndex getMBBEndIdx(unsigned Num) const {
return getMBBRange(Num).second;
}

/// Returns the last index in the given basic block.
/// Returns the index past the last valid index in the given basic block.
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
return getMBBRange(mbb).second;
}

/// Returns the last valid index in the given basic block.
/// This index corresponds to the dead slot of the last non-debug
/// instruction and can be used to find live-out ranges of the block. Note
/// that getMBBEndIdx returns the start index of the next block, which is
/// also used as the start index for segments with phi-def values. If the
/// basic block doesn't contain any non-debug instructions, this returns
/// the same as getMBBStartIdx.getDeadSlot().
SlotIndex getMBBLastIdx(const MachineBasicBlock *MBB) const {
return getMBBEndIdx(MBB).getPrevSlot();
}

/// Iterator over the idx2MBBMap (sorted pairs of slot index of basic block
/// begin and basic block)
using MBBIndexIterator = SmallVectorImpl<IdxMBBPair>::const_iterator;
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8 changes: 4 additions & 4 deletions llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
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Expand Up @@ -905,7 +905,7 @@ bool GCNRegPressurePrinter::runOnMachineFunction(MachineFunction &MF) {
OS << ":\n";

SlotIndex MBBStartSlot = LIS.getSlotIndexes()->getMBBStartIdx(&MBB);
SlotIndex MBBEndSlot = LIS.getSlotIndexes()->getMBBEndIdx(&MBB);
SlotIndex MBBLastSlot = LIS.getSlotIndexes()->getMBBLastIdx(&MBB);

GCNRPTracker::LiveRegSet LiveIn, LiveOut;
GCNRegPressure RPAtMBBEnd;
Expand All @@ -931,7 +931,7 @@ bool GCNRegPressurePrinter::runOnMachineFunction(MachineFunction &MF) {
}
} else {
GCNUpwardRPTracker RPT(LIS);
RPT.reset(MRI, MBBEndSlot);
RPT.reset(MRI, MBBLastSlot);

LiveOut = RPT.getLiveRegs();
RPAtMBBEnd = RPT.getPressure();
Expand Down Expand Up @@ -966,14 +966,14 @@ bool GCNRegPressurePrinter::runOnMachineFunction(MachineFunction &MF) {

OS << PFX " Live-out:" << llvm::print(LiveOut, MRI);
if (UseDownwardTracker)
ReportLISMismatchIfAny(LiveOut, getLiveRegs(MBBEndSlot, LIS, MRI));
ReportLISMismatchIfAny(LiveOut, getLiveRegs(MBBLastSlot, LIS, MRI));

GCNRPTracker::LiveRegSet LiveThrough;
for (auto [Reg, Mask] : LiveIn) {
LaneBitmask MaskIntersection = Mask & LiveOut.lookup(Reg);
if (MaskIntersection.any()) {
LaneBitmask LTMask = getRegLiveThroughMask(
MRI, LIS, Reg, MBBStartSlot, MBBEndSlot, MaskIntersection);
MRI, LIS, Reg, MBBStartSlot, MBBLastSlot, MaskIntersection);
if (LTMask.any())
LiveThrough[Reg] = LTMask;
}
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4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/GCNRegPressure.h
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Expand Up @@ -313,8 +313,8 @@ class GCNUpwardRPTracker : public GCNRPTracker {

/// reset tracker to the end of the \p MBB.
void reset(const MachineBasicBlock &MBB) {
reset(MBB.getParent()->getRegInfo(),
LIS.getSlotIndexes()->getMBBEndIdx(&MBB));
SlotIndex MBBLastSlot = LIS.getSlotIndexes()->getMBBLastIdx(&MBB);
reset(MBB.getParent()->getRegInfo(), MBBLastSlot);
}

/// reset tracker to the point just after \p MI (in program order).
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18 changes: 8 additions & 10 deletions llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
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Expand Up @@ -510,14 +510,14 @@ body: |
; RPU-NEXT: 0 0 $sgpr0 = S_BUFFER_LOAD_DWORD_IMM $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0
; RPU-NEXT: 0 0
; RPU-NEXT: 0 1 undef %0.sub5:vreg_512 = V_MOV_B32_e32 5, implicit $exec
; RPU-NEXT: 0 0
; RPU-NEXT: 0 0 S_CMP_GT_U32 $sgpr0, 15, implicit-def $scc
; RPU-NEXT: 0 0
; RPU-NEXT: 0 0 S_CBRANCH_SCC1 %bb.2, implicit $scc
; RPU-NEXT: 0 0
; RPU-NEXT: 0 0 S_BRANCH %bb.1
; RPU-NEXT: 0 0
; RPU-NEXT: Live-out:
; RPU-NEXT: 0 1
; RPU-NEXT: 0 1 S_CMP_GT_U32 $sgpr0, 15, implicit-def $scc
; RPU-NEXT: 0 1
; RPU-NEXT: 0 1 S_CBRANCH_SCC1 %bb.2, implicit $scc
; RPU-NEXT: 0 1
; RPU-NEXT: 0 1 S_BRANCH %bb.1
; RPU-NEXT: 0 1
; RPU-NEXT: Live-out: %0:0000000000000C00
; RPU-NEXT: Live-thr:
; RPU-NEXT: 0 0
; RPU-NEXT: bb.1:
Expand Down Expand Up @@ -571,8 +571,6 @@ body: |
; RPD-NEXT: 0 1 S_BRANCH %bb.1
; RPD-NEXT: 0 1
; RPD-NEXT: Live-out: %0:0000000000000C00
; RPD-NEXT: mis LIS:
; RPD-NEXT: %0:L0000000000000C00 isn't found in LIS reported set
; RPD-NEXT: Live-thr:
; RPD-NEXT: 0 0
; RPD-NEXT: bb.1:
Expand Down