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[RISCV] Replace uses of RISCV::NoRegister with Register() or isValid. NFC #161781

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Merged
merged 2 commits into from
Oct 3, 2025
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[RISCV] Replace uses of RISCV::NoRegister with Register() or isValid. NFC #161781

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[RISCV] Replace uses of RISCV::NoRegister with Register(), isValid(),…
topperc Oct 3, 2025
6440e16
fixup! consistently use isValid.
topperc Oct 3, 2025
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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1560,7 +1560,7 @@ static MCRegister getRVVBaseRegister(const RISCVRegisterInfo &TRI,
MCRegister BaseReg = TRI.getSubReg(Reg, RISCV::sub_vrm1_0);
// If it's not a grouped vector register, it doesn't have subregister, so
// the base register is just itself.
if (BaseReg == RISCV::NoRegister)
if (!BaseReg)
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@lenary lenary Oct 3, 2025

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Quibble - MCRegister doesn't have an operator bool, you're using the operator unsigned here, and then assuming that NoRegister has falsey value - but using RISCV::NoRegister is a way to remove that assumption, or you could do the following:

Suggested change
if (!BaseReg)
if (!BaseReg.isValid())

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@topperc topperc Oct 3, 2025

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In my prior conversations with @arsenm, I think we decided that we will add an operator bool when we remove operator unsigned.

BaseReg = Reg;
return BaseReg;
}
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6 changes: 3 additions & 3 deletions llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
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Expand Up @@ -128,7 +128,7 @@ static bool hasUndefinedPassthru(const MachineInstr &MI) {
// All undefined passthrus should be $noreg: see
// RISCVDAGToDAGISel::doPeepholeNoRegPassThru
const MachineOperand &UseMO = MI.getOperand(UseOpIdx);
return UseMO.getReg() == RISCV::NoRegister || UseMO.isUndef();
return !UseMO.getReg() || UseMO.isUndef();
}

/// Return true if \p MI is a copy that will be lowered to one or more vmvNr.vs.
Expand Down Expand Up @@ -1454,7 +1454,7 @@ void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) {
Register Reg = VLOp.getReg();

// Erase the AVL operand from the instruction.
VLOp.setReg(RISCV::NoRegister);
VLOp.setReg(Register());
VLOp.setIsKill(false);
if (LIS) {
LiveInterval &LI = LIS->getInterval(Reg);
Expand Down Expand Up @@ -1663,7 +1663,7 @@ void RISCVInsertVSETVLI::coalesceVSETVLIs(MachineBasicBlock &MBB) const {
if (!MO.isReg() || !MO.getReg().isVirtual())
return;
Register OldVLReg = MO.getReg();
MO.setReg(RISCV::NoRegister);
MO.setReg(Register());

if (LIS)
LIS->shrinkToUses(&LIS->getInterval(OldVLReg));
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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Expand Up @@ -1364,7 +1364,7 @@ void RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
RS->scavengeRegisterBackwards(RISCV::GPRRegClass, MI.getIterator(),
/*RestoreAfter=*/false, /*SpAdj=*/0,
/*AllowSpill=*/false);
if (TmpGPR != RISCV::NoRegister)
if (TmpGPR)
RS->setRegUsed(TmpGPR);
else {
// The case when there is no scavenged register needs special handling.
Expand Down Expand Up @@ -3021,7 +3021,7 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
ErrInfo = "Invalid operand type for VL operand";
return false;
}
if (Op.isReg() && Op.getReg() != RISCV::NoRegister) {
if (Op.isReg() && Op.getReg().isValid()) {
const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
auto *RC = MRI.getRegClass(Op.getReg());
if (!RISCV::GPRRegClass.hasSubClassEq(RC)) {
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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
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Expand Up @@ -259,7 +259,7 @@ static RegImmPair getRegImmPairPreventingCompression(const MachineInstr &MI) {
if (isCompressibleLoad(MI) || isCompressibleStore(MI)) {
const MachineOperand &MOImm = MI.getOperand(2);
if (!MOImm.isImm())
return RegImmPair(RISCV::NoRegister, 0);
return RegImmPair(Register(), 0);

int64_t Offset = MOImm.getImm();
int64_t NewBaseAdjust = getBaseAdjustForCompression(Offset, Opcode);
Expand Down Expand Up @@ -292,7 +292,7 @@ static RegImmPair getRegImmPairPreventingCompression(const MachineInstr &MI) {
}
}
}
return RegImmPair(RISCV::NoRegister, 0);
return RegImmPair(Register(), 0);
}

// Check all uses after FirstMI of the given register, keeping a vector of
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16 changes: 8 additions & 8 deletions llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
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Expand Up @@ -382,7 +382,7 @@ bool RISCVVectorPeephole::convertAllOnesVMergeToVMv(MachineInstr &MI) const {
// vmv.v.v doesn't have a mask operand, so we may be able to inflate the
// register class for the destination and passthru operands e.g. VRNoV0 -> VR
MRI->recomputeRegClass(MI.getOperand(0).getReg());
if (MI.getOperand(1).getReg() != RISCV::NoRegister)
if (MI.getOperand(1).getReg())
MRI->recomputeRegClass(MI.getOperand(1).getReg());
return true;
}
Expand Down Expand Up @@ -448,7 +448,7 @@ bool RISCVVectorPeephole::convertSameMaskVMergeToVMv(MachineInstr &MI) {
Register FalseReg = MI.getOperand(2).getReg();
if (TruePassthruReg != FalseReg) {
// If True's passthru is undef see if we can change it to False
if (TruePassthruReg != RISCV::NoRegister ||
if (TruePassthruReg.isValid() ||
!MRI->hasOneUse(MI.getOperand(3).getReg()) ||
!ensureDominates(MI.getOperand(2), *True))
return false;
Expand All @@ -467,7 +467,7 @@ bool RISCVVectorPeephole::convertSameMaskVMergeToVMv(MachineInstr &MI) {
// vmv.v.v doesn't have a mask operand, so we may be able to inflate the
// register class for the destination and passthru operands e.g. VRNoV0 -> VR
MRI->recomputeRegClass(MI.getOperand(0).getReg());
if (MI.getOperand(1).getReg() != RISCV::NoRegister)
if (MI.getOperand(1).getReg())
MRI->recomputeRegClass(MI.getOperand(1).getReg());
return true;
}
Expand Down Expand Up @@ -517,7 +517,7 @@ bool RISCVVectorPeephole::convertToUnmasked(MachineInstr &MI) const {
if (RISCVII::isFirstDefTiedToFirstUse(MaskedMCID)) {
unsigned PassthruOpIdx = MI.getNumExplicitDefs();
if (HasPassthru) {
if (MI.getOperand(PassthruOpIdx).getReg() != RISCV::NoRegister)
if (MI.getOperand(PassthruOpIdx).getReg())
MRI->recomputeRegClass(MI.getOperand(PassthruOpIdx).getReg());
} else
MI.removeOperand(PassthruOpIdx);
Expand Down Expand Up @@ -576,7 +576,7 @@ static bool dominates(MachineBasicBlock::const_iterator A,
bool RISCVVectorPeephole::ensureDominates(const MachineOperand &MO,
MachineInstr &Src) const {
assert(MO.getParent()->getParent() == Src.getParent());
if (!MO.isReg() || MO.getReg() == RISCV::NoRegister)
if (!MO.isReg() || !MO.getReg())
return true;

MachineInstr *Def = MRI->getVRegDef(MO.getReg());
Expand All @@ -593,7 +593,7 @@ bool RISCVVectorPeephole::ensureDominates(const MachineOperand &MO,
bool RISCVVectorPeephole::foldUndefPassthruVMV_V_V(MachineInstr &MI) {
if (RISCV::getRVVMCOpcode(MI.getOpcode()) != RISCV::VMV_V_V)
return false;
if (MI.getOperand(1).getReg() != RISCV::NoRegister)
if (MI.getOperand(1).getReg().isValid())
return false;

// If the input was a pseudo with a policy operand, we can give it a tail
Expand Down Expand Up @@ -654,7 +654,7 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {

// Src needs to have the same passthru as VMV_V_V
MachineOperand &SrcPassthru = Src->getOperand(Src->getNumExplicitDefs());
if (SrcPassthru.getReg() != RISCV::NoRegister &&
if (SrcPassthru.getReg().isValid() &&
SrcPassthru.getReg() != Passthru.getReg())
return false;

Expand All @@ -672,7 +672,7 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
if (SrcPassthru.getReg() != Passthru.getReg()) {
SrcPassthru.setReg(Passthru.getReg());
// If Src is masked then its passthru needs to be in VRNoV0.
if (Passthru.getReg() != RISCV::NoRegister)
if (Passthru.getReg())
MRI->constrainRegClass(
Passthru.getReg(),
TII->getRegClass(Src->getDesc(), SrcPassthru.getOperandNo(), TRI));
Expand Down