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[RISCV][GISel] Add manual instruction selection for i8/i16/i32->i32/i64 G_SEXT/G_ZEXT. #161971

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Merged
merged 2 commits into from
Oct 8, 2025
Merged

[RISCV][GISel] Add manual instruction selection for i8/i16/i32->i32/i64 G_SEXT/G_ZEXT. #161971

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5379dfa
[RISCV][GISel] Add manual instruction selection for i8/i16/i32->i32/i…
topperc Oct 3, 2025
4c4b8c4
Merge remote-tracking branch 'origin/main' into pr/gisel-sext-zext
topperc Oct 7, 2025
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56 changes: 56 additions & 0 deletions llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -736,6 +736,62 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
MI.eraseFromParent();
return true;
}
case TargetOpcode::G_ZEXT:
case TargetOpcode::G_SEXT: {
bool IsSigned = Opc != TargetOpcode::G_ZEXT;
Register DstReg = MI.getOperand(0).getReg();
Register SrcReg = MI.getOperand(1).getReg();
LLT SrcTy = MRI->getType(SrcReg);
unsigned SrcSize = SrcTy.getSizeInBits();

if (SrcTy.isVector())
return false; // Should be handled by imported patterns.

assert((*RBI.getRegBank(DstReg, *MRI, TRI)).getID() ==
RISCV::GPRBRegBankID &&
"Unexpected ext regbank");

// Use addiw SrcReg, 0 (sext.w) for i32.
if (IsSigned && SrcSize == 32) {
MI.setDesc(TII.get(RISCV::ADDIW));
MI.addOperand(MachineOperand::CreateImm(0));
return constrainSelectedInstRegOperands(MI, TII, TRI, RBI);
}

// Use add.uw SrcReg, X0 (zext.w) for i32 with Zba.
if (!IsSigned && SrcSize == 32 && STI.hasStdExtZba()) {
MI.setDesc(TII.get(RISCV::ADD_UW));
MI.addOperand(MachineOperand::CreateReg(RISCV::X0, /*isDef=*/false));
return constrainSelectedInstRegOperands(MI, TII, TRI, RBI);
}

// Use sext.h/zext.h for i16 with Zbb.
if (SrcSize == 16 && STI.hasStdExtZbb()) {
MI.setDesc(TII.get(IsSigned ? RISCV::SEXT_H
: STI.isRV64() ? RISCV::ZEXT_H_RV64
: RISCV::ZEXT_H_RV32));
return constrainSelectedInstRegOperands(MI, TII, TRI, RBI);
}

// Use pack(w) SrcReg, X0 for i16 zext with Zbkb.
if (!IsSigned && SrcSize == 16 && STI.hasStdExtZbkb()) {
MI.setDesc(TII.get(STI.is64Bit() ? RISCV::PACKW : RISCV::PACK));
MI.addOperand(MachineOperand::CreateReg(RISCV::X0, /*isDef=*/false));
return constrainSelectedInstRegOperands(MI, TII, TRI, RBI);
}

// Fall back to shift pair.
auto ShiftLeft =
MIB.buildInstr(RISCV::SLLI, {&RISCV::GPRRegClass}, {SrcReg})
.addImm(STI.getXLen() - SrcSize);
constrainSelectedInstRegOperands(*ShiftLeft, TII, TRI, RBI);
auto ShiftRight = MIB.buildInstr(IsSigned ? RISCV::SRAI : RISCV::SRLI,
{DstReg}, {ShiftLeft})
.addImm(STI.getXLen() - SrcSize);
constrainSelectedInstRegOperands(*ShiftRight, TII, TRI, RBI);
MI.eraseFromParent();
return true;
}
case TargetOpcode::G_FCONSTANT: {
// TODO: Use constant pool for complex constants.
Register DstReg = MI.getOperand(0).getReg();
Expand Down
54 changes: 0 additions & 54 deletions llvm/lib/Target/RISCV/RISCVGISel.td
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Expand Up @@ -133,60 +133,6 @@ def : LdPat<extloadi16, LH, i32>;
def : StPat<truncstorei8, SB, GPR, i32>;
def : StPat<truncstorei16, SH, GPR, i32>;

def : Pat<(sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>;

def : Pat<(sext_inreg (i64 (add GPR:$rs1, simm12_lo:$imm)), i32),
(ADDIW GPR:$rs1, simm12_lo:$imm)>;
}

let Predicates = [IsRV64, NoStdExtZba] in
def : Pat<(zext (i32 GPR:$src)), (SRLI (i64 (SLLI GPR:$src, 32)), 32)>;

let Predicates = [IsRV32, NoStdExtZbb, NoStdExtZbkb] in
def : Pat<(XLenVT (zext (i16 GPR:$src))),
(SRLI (XLenVT (SLLI GPR:$src, 16)), 16)>;

let Predicates = [IsRV64, NoStdExtZbb, NoStdExtZbkb] in {
def : Pat<(i64 (zext (i16 GPR:$src))),
(SRLI (XLenVT (SLLI GPR:$src, 48)), 48)>;
def : Pat<(i32 (zext (i16 GPR:$src))),
(SRLI (XLenVT (SLLI GPR:$src, 48)), 48)>;
}

let Predicates = [IsRV32, NoStdExtZbb] in
def : Pat<(XLenVT (sext (i16 GPR:$src))),
(SRAI (XLenVT (SLLI GPR:$src, 16)), 16)>;

let Predicates = [IsRV64, NoStdExtZbb] in {
def : Pat<(i64 (sext (i16 GPR:$src))),
(SRAI (XLenVT (SLLI GPR:$src, 48)), 48)>;
def : Pat<(i32 (sext (i16 GPR:$src))),
(SRAI (XLenVT (SLLI GPR:$src, 48)), 48)>;
}

//===----------------------------------------------------------------------===//
// Zb* RV64 patterns not used by SelectionDAG.
//===----------------------------------------------------------------------===//

let Predicates = [HasStdExtZba, IsRV64] in {
def : Pat<(zext (i32 GPR:$src)), (ADD_UW GPR:$src, (XLenVT X0))>;
}

let Predicates = [HasStdExtZbb] in
def : Pat<(i32 (sext (i16 GPR:$rs))), (SEXT_H GPR:$rs)>;
let Predicates = [HasStdExtZbb, IsRV64] in
def : Pat<(i64 (sext (i16 GPR:$rs))), (SEXT_H GPR:$rs)>;

let Predicates = [HasStdExtZbb, IsRV32] in
def : Pat<(i32 (zext (i16 GPR:$rs))), (ZEXT_H_RV32 GPR:$rs)>;
let Predicates = [HasStdExtZbb, IsRV64] in {
def : Pat<(i64 (zext (i16 GPR:$rs))), (ZEXT_H_RV64 GPR:$rs)>;
def : Pat<(i32 (zext (i16 GPR:$rs))), (ZEXT_H_RV64 GPR:$rs)>;
}

let Predicates = [HasStdExtZbkb, NoStdExtZbb, IsRV32] in
def : Pat<(i32 (zext (i16 GPR:$rs))), (PACK GPR:$rs, (XLenVT X0))>;
let Predicates = [HasStdExtZbkb, NoStdExtZbb, IsRV64] in {
def : Pat<(i64 (zext (i16 GPR:$rs))), (PACKW GPR:$rs, (XLenVT X0))>;
def : Pat<(i32 (zext (i16 GPR:$rs))), (PACKW GPR:$rs, (XLenVT X0))>;
}
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