[RISCV][llvm] Preliminary P extension codegen support

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

@@ -79,6 +79,32 @@ static void generateInstSeqImpl(int64_t Val, const MCSubtargetInfo &STI,
     }
   }
 
+  if (STI.hasFeature(RISCV::FeatureStdExtP)) {
+    // Check if the immediate is packed i8 or i10
+    int32_t Bit63To32 = Val >> 32;
+    int32_t Bit31To0 = Val & 0xFFFFFFFF;
+    int16_t Bit31To16 = Bit31To0 >> 16;
+    int16_t Bit15To0 = Bit31To0 & 0xFFFF;
+    int8_t Bit15To8 = Bit15To0 >> 8;
+    int8_t Bit7To0 = Bit15To0 & 0xFF;
+    if (Bit63To32 == Bit31To0) {
+      if (IsRV64 && isInt<10>(Bit63To32)) {
+        Res.emplace_back(RISCV::PLI_W, Bit63To32);
+        return;
+      }
+      if (Bit31To16 == Bit15To0) {
+        if (isInt<10>(Bit31To16)) {
+          Res.emplace_back(RISCV::PLI_H, Bit31To16);
+          return;
+        }
+        if (Bit15To8 == Bit7To0) {
+          Res.emplace_back(RISCV::PLI_B, Bit15To8);
+          return;
+        }
+      }
+    }
+  }
+
   if (isInt<32>(Val)) {
     // Depending on the active bits in the immediate Value v, the following
     // instruction sequences are emitted:
@@ -562,6 +588,9 @@ OpndKind Inst::getOpndKind() const {
   case RISCV::LUI:
   case RISCV::QC_LI:
   case RISCV::QC_E_LI:
+  case RISCV::PLI_B:
+  case RISCV::PLI_H:
+  case RISCV::PLI_W:
     return RISCVMatInt::Imm;
   case RISCV::ADD_UW:
     return RISCVMatInt::RegX0;

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h

@@ -21,7 +21,7 @@ namespace RISCVMatInt {
 
 enum OpndKind {
   RegImm, // ADDI/ADDIW/XORI/SLLI/SRLI/SLLI_UW/RORI/BSETI/BCLRI/TH_SRRI
-  Imm,    // LUI/QC_LI/QC_E_LI
+  Imm,    // LUI/QC_LI/QC_E_LI/PLI_B/PLI_H/PLI_W
   RegReg, // SH1ADD/SH2ADD/SH3ADD/PACK
   RegX0,  // ADD_UW
 };

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

@@ -1034,6 +1034,14 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     if (!isInt<32>(Imm) && isUInt<32>(Imm) && hasAllWUsers(Node))
       Imm = SignExtend64<32>(Imm);
 
+    if (hasAllWUsers(Node) && Subtarget->hasStdExtP() &&
+        Subtarget->enablePExtCodeGen()) {
+      // If its 4 packed 8 bit integer or 2 packed signed integer, we can simply
+      // copy lower 32 bits to higher 32 bits to make it able to rematerialize
+      // to PLI_B or PLI_H
+      Imm = (Imm << 32) | (Imm & 0xFFFFFFFF);
+    }
+
     ReplaceNode(Node, selectImm(CurDAG, DL, VT, Imm, *Subtarget).getNode());
     return;
   }

llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll

@@ -422,55 +422,34 @@ define void @test_pasubu_b(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
 
 ; Test PLI (pack load immediate) for v2i16
 define void @test_pli_h(ptr %ret_ptr) {
-; CHECK-RV32-LABEL: test_pli_h:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    pli.h a1, 42
-; CHECK-RV32-NEXT:    sw a1, 0(a0)
-; CHECK-RV32-NEXT:    ret
-;
-; CHECK-RV64-LABEL: test_pli_h:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    lui a1, 672
-; CHECK-RV64-NEXT:    addi a1, a1, 42
-; CHECK-RV64-NEXT:    sw a1, 0(a0)
-; CHECK-RV64-NEXT:    ret
+; CHECK-LABEL: test_pli_h:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pli.h a1, 42
+; CHECK-NEXT:    sw a1, 0(a0)
+; CHECK-NEXT:    ret
   %res = add <2 x i16> <i16 42, i16 42>, <i16 0, i16 0>
   store <2 x i16> %res, ptr %ret_ptr
   ret void
 }
 
 define void @test_pli_h_negative(ptr %ret_ptr) {
-; CHECK-RV32-LABEL: test_pli_h_negative:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    pli.h a1, -5
-; CHECK-RV32-NEXT:    sw a1, 0(a0)
-; CHECK-RV32-NEXT:    ret
-;
-; CHECK-RV64-LABEL: test_pli_h_negative:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    lui a1, 1048512
-; CHECK-RV64-NEXT:    addi a1, a1, -5
-; CHECK-RV64-NEXT:    sw a1, 0(a0)
-; CHECK-RV64-NEXT:    ret
+; CHECK-LABEL: test_pli_h_negative:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pli.h a1, -5
+; CHECK-NEXT:    sw a1, 0(a0)
+; CHECK-NEXT:    ret
   %res = add <2 x i16> <i16 -5, i16 -5>, <i16 0, i16 0>
   store <2 x i16> %res, ptr %ret_ptr
   ret void
 }
 
 ; Test PLI for v4i8 with unsigned immediate
 define void @test_pli_b(ptr %ret_ptr) {
-; CHECK-RV32-LABEL: test_pli_b:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    pli.b a1, 32
-; CHECK-RV32-NEXT:    sw a1, 0(a0)
-; CHECK-RV32-NEXT:    ret
-;
-; CHECK-RV64-LABEL: test_pli_b:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    lui a1, 131586
-; CHECK-RV64-NEXT:    addi a1, a1, 32
-; CHECK-RV64-NEXT:    sw a1, 0(a0)
-; CHECK-RV64-NEXT:    ret
+; CHECK-LABEL: test_pli_b:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pli.b a1, 32
+; CHECK-NEXT:    sw a1, 0(a0)
+; CHECK-NEXT:    ret
   %res = add <4 x i8> <i8 32, i8 32, i8 32, i8 32>, <i8 0, i8 0, i8 0, i8 0>
   store <4 x i8> %res, ptr %ret_ptr
   ret void
@@ -485,8 +464,7 @@ define void @test_pli_b_negative(ptr %ret_ptr) {
 ;
 ; CHECK-RV64-LABEL: test_pli_b_negative:
 ; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    lui a1, 1044464
-; CHECK-RV64-NEXT:    addi a1, a1, -258
+; CHECK-RV64-NEXT:    pli.h a1, -258
 ; CHECK-RV64-NEXT:    sw a1, 0(a0)
 ; CHECK-RV64-NEXT:    ret
   %res = add <4 x i8> <i8 -2, i8 -2, i8 -2, i8 -2>, <i8 0, i8 0, i8 0, i8 0>