[RISCV][llvm] Preliminary P extension codegen support

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

@@ -809,6 +809,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
 
   bool isSImm5() const { return isSImm<5>(); }
   bool isSImm6() const { return isSImm<6>(); }
+  bool isSImm8() const { return isSImm<8>(); }
   bool isSImm10() const { return isSImm<10>(); }
   bool isSImm11() const { return isSImm<11>(); }
   bool isSImm12() const { return isSImm<12>(); }

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

@@ -79,6 +79,32 @@ static void generateInstSeqImpl(int64_t Val, const MCSubtargetInfo &STI,
     }
   }
 
+  if (STI.hasFeature(RISCV::FeatureStdExtP)) {
+    // Check if the immediate is packed i8 or i10
+    int32_t Bit63To32 = Val >> 32;
+    int32_t Bit31To0 = Val & 0xFFFFFFFF;
+    int16_t Bit31To16 = Bit31To0 >> 16;
+    int16_t Bit15To0 = Bit31To0 & 0xFFFF;
+    int8_t Bit15To8 = Bit15To0 >> 8;
+    int8_t Bit7To0 = Bit15To0 & 0xFF;
+    if (Bit63To32 == Bit31To0) {
+      if (IsRV64 && isInt<10>(Bit63To32)) {
+        Res.emplace_back(RISCV::PLI_W, Bit63To32);
+        return;
+      }
+      if (Bit31To16 == Bit15To0) {
+        if (isInt<10>(Bit31To16)) {
+          Res.emplace_back(RISCV::PLI_H, Bit31To16);
+          return;
+        }
+        if (Bit15To8 == Bit7To0) {
+          Res.emplace_back(RISCV::PLI_B, Bit15To8);
+          return;
+        }
+      }
+    }
+  }
+
   if (isInt<32>(Val)) {
     // Depending on the active bits in the immediate Value v, the following
     // instruction sequences are emitted:
@@ -562,6 +588,9 @@ OpndKind Inst::getOpndKind() const {
   case RISCV::LUI:
   case RISCV::QC_LI:
   case RISCV::QC_E_LI:
+  case RISCV::PLI_B:
+  case RISCV::PLI_H:
+  case RISCV::PLI_W:
     return RISCVMatInt::Imm;
   case RISCV::ADD_UW:
     return RISCVMatInt::RegX0;

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h

@@ -21,7 +21,7 @@ namespace RISCVMatInt {
 
 enum OpndKind {
   RegImm, // ADDI/ADDIW/XORI/SLLI/SRLI/SLLI_UW/RORI/BSETI/BCLRI/TH_SRRI
-  Imm,    // LUI/QC_LI/QC_E_LI
+  Imm,    // LUI/QC_LI/QC_E_LI/PLI_B/PLI_H/PLI_W
   RegReg, // SH1ADD/SH2ADD/SH3ADD/PACK
   RegX0,  // ADD_UW
 };

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -1104,6 +1104,10 @@ def FeatureStdExtP
 def HasStdExtP : Predicate<"Subtarget->hasStdExtP()">,
                  AssemblerPredicate<(all_of FeatureStdExtP),
                                     "'Base P' (Packed SIMD)">;
+def FeatureEnablePExtCodeGen
+    : SubtargetFeature<"enable-p-ext-codegen", "EnablePExtCodeGen",
+                       "true", "Turn on P Extension codegen(This is a temporary"
+                       " switch where only partial codegen is currently supported)">;
 
 def HasStdExtZbaOrP
     : Predicate<"Subtarget->hasStdExtZba() || Subtarget->hasStdExtP()">,

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

@@ -1034,6 +1034,14 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     if (!isInt<32>(Imm) && isUInt<32>(Imm) && hasAllWUsers(Node))
       Imm = SignExtend64<32>(Imm);
 
+    if (hasAllWUsers(Node) && Subtarget->hasStdExtP() &&
+        Subtarget->enablePExtCodeGen()) {
+      // If its 4 packed 8 bit integer or 2 packed signed integer, we can simply
+      // copy lower 32 bits to higher 32 bits to make it able to rematerialize
+      // to PLI_B or PLI_H
+      Imm = (Imm << 32) | (Imm & 0xFFFFFFFF);
+    }
+
     ReplaceNode(Node, selectImm(CurDAG, DL, VT, Imm, *Subtarget).getNode());
     return;
   }
@@ -2654,6 +2662,14 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
       CurDAG->RemoveDeadNode(Node);
       return;
     }
+    if (Subtarget->hasStdExtP() && Subtarget->enablePExtCodeGen()) {
+      if (((VT == MVT::v4i16 || VT == MVT::v8i8) && SrcVT == MVT::i64) ||
+          ((SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) && VT == MVT::i64)) {
+        ReplaceUses(SDValue(Node, 0), Node->getOperand(0));
+        CurDAG->RemoveDeadNode(Node);
+      }
+      return;
+    }
     break;
   }
   case ISD::INSERT_SUBVECTOR: