Skip to content

[PowerPC] Update tlbie instruction implementation for ISA3.0+ #162729

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 3 commits into
base: main
Choose a base branch
from
Open

[PowerPC] Update tlbie instruction implementation for ISA3.0+ #162729

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
3f055e2
[PowerPC] Update instruction implementation for ISA3.0+
lei137 Oct 9, 2025
1b6e0ab
remove unnecessary lines
lei137 Oct 9, 2025
976ee02
Update changes due to scheduling.
lei137 Oct 14, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
13 changes: 5 additions & 8 deletions llvm/lib/Target/PowerPC/P10InstrResources.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -825,17 +825,15 @@ def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read, P10F2_Read, P10F2_Read],
def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_DISP_ANY, P10F2_Read],
(instrs
SRADI_rec,
SRAWI_rec,
SRAWI8_rec
Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Note this is an auto generated file.

SRAWI8_rec, SRAWI_rec
)>;

// Single crack instructions
// 4 Cycles ALU2 operations, 2 input operands
def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_DISP_ANY, P10F2_Read, P10F2_Read],
(instrs
SRAD_rec,
SRAW_rec,
SRAW8_rec
SRAW8_rec, SRAW_rec
)>;

// 2-way crack instructions
Expand Down Expand Up @@ -883,7 +881,7 @@ def : InstRW<[P10W_FX_3C, P10W_DISP_ANY],
// 3 Cycles ALU operations, 1 input operands
def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read],
(instrs
ADDI, ADDI8, ADDIdtprelL32, ADDItlsldLADDR32, ADDItocL, ADDItocL8, LI, LI8,
ADDI, ADDI8, ADDIdtprelL32, ADDItlsldLADDR32, ADDItocL, LI, LI8,
ADDIC, ADDIC8,
ADDIS, ADDIS8, ADDISdtprelHA32, ADDIStocHA, ADDIStocHA8, LIS, LIS8,
ADDME, ADDME8,
Expand Down Expand Up @@ -1864,7 +1862,7 @@ def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10ST_Read, P10ST_Read]
(instrs
CP_PASTE8_rec, CP_PASTE_rec,
SLBIEG,
TLBIE
TLBIE, TLBIE8P9, TLBIEP9
)>;

// Single crack instructions
Expand All @@ -1886,8 +1884,7 @@ def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10ST_Read, P10ST_Read,
def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY],
(instrs
ISYNC,
SYNCP10,
SYNC
SYNC, SYNCP10
)>;

// Expand instructions
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/PowerPC/P9InstrResources.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -905,7 +905,7 @@ def : InstRW<[P9_LS_1C, IP_EXEC_1C, IP_AGEN_1C, DISP_3SLOTS_1C],
SLBIEG,
STMW,
STSWI,
TLBIE
TLBIE, TLBIEP9, TLBIE8P9
)>;

// Vector Store Instruction
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/PowerPC/PPC.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -409,6 +409,7 @@ def HasP10Vector : Predicate<"Subtarget->hasP10Vector()">;
def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">;
def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">;
def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">;
def IsNotISA3_0 : Predicate<"!Subtarget->isISA3_0()">;
def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
def IsNotISA3_1 : Predicate<"!Subtarget->isISA3_1()">;
def IsISAFuture : Predicate<"Subtarget->isISAFuture()">;
Expand Down
8 changes: 6 additions & 2 deletions llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@ FUSION_FEATURE(GeneralBack2Back, hasBack2BackFusion, -1,
ADDIStocHA8,
ADDIdtprelL32,
ADDItlsldLADDR32,
ADDItocL8,
Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Note this is an auto generated file.

ADDItocL,
ADDME,
ADDME8,
ADDME8O,
Expand Down Expand Up @@ -209,7 +209,9 @@ FUSION_FEATURE(GeneralBack2Back, hasBack2BackFusion, -1,
SRADI,
SRADI_32,
SRAW,
SRAW8,
SRAWI,
SRAWI8,
SRD,
SRD_rec,
SRW,
Expand Down Expand Up @@ -518,7 +520,7 @@ FUSION_FEATURE(GeneralBack2Back, hasBack2BackFusion, -1,
ADDIStocHA8,
ADDIdtprelL32,
ADDItlsldLADDR32,
ADDItocL8,
ADDItocL,
ADDME,
ADDME8,
ADDME8O,
Expand Down Expand Up @@ -747,7 +749,9 @@ FUSION_FEATURE(GeneralBack2Back, hasBack2BackFusion, -1,
SRADI,
SRADI_32,
SRAW,
SRAW8,
SRAWI,
SRAWI8,
SRD,
SRD_rec,
SRW,
Expand Down
20 changes: 20 additions & 0 deletions llvm/lib/Target/PowerPC/PPCInstrFormats.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -850,6 +850,26 @@ class XForm_45<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
let Inst{31} = 0;
}

class XForm_RSB5_UIMM2_2UIMM1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmstr, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, NoItinerary> {

bits<5> RS;
bits<5> RB;
bits<2> RIC;
bits<1> PRS;
bits<1> R;

let Pattern = pattern;

let Inst{6...10} = RS;
let Inst{12...13} = RIC;
let Inst{14} = PRS;
let Inst{15} = R;
let Inst{16...20} = RB;
let Inst{21...30} = xo;
}

class X_FRT5_XO2_XO3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, bits<10> xo,
dag OOL, dag IOL, string asmstr, InstrItinClass itin,
list<dag> pattern>
Expand Down
23 changes: 21 additions & 2 deletions llvm/lib/Target/PowerPC/PPCInstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4321,7 +4321,22 @@ def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
"tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;

def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RST, gprc:$RB),
"tlbie $RB,$RST", IIC_SprTLBIE, []>;
"tlbie $RB, $RST", IIC_SprTLBIE, []>,
Requires<[IsNotISA3_0]>;

let Predicates = [IsISA3_0] in {
def TLBIEP9 : XForm_RSB5_UIMM2_2UIMM1<31, 306, (outs),
(ins gprc:$RB, gprc:$RS, u2imm:$RIC,
u1imm:$PRS, u1imm:$R),
"tlbie $RB, $RS, $RIC, $PRS, $R", []>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
def TLBIE8P9
: XForm_RSB5_UIMM2_2UIMM1<31, 306, (outs),
(ins g8rc:$RB, g8rc:$RS, u2imm:$RIC,
u1imm:$PRS, u1imm:$R),
"tlbie $RB, $RS, $RIC, $PRS, $R", []>;
}
}

def TLBSX : XForm_tlb<914, (outs), (ins gprc:$RA, gprc:$RB), "tlbsx $RA, $RB",
IIC_LdStLoad>, Requires<[IsBookE]>;
Expand Down Expand Up @@ -4667,7 +4682,11 @@ def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;

}

def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>, Requires<[IsNotISA3_0]>;
let Predicates = [IsISA3_0] in {
def : InstAlias<"tlbie $RB", (TLBIEP9 R0, gprc:$RB, 0, 0, 0)>;
def : InstAlias<"tlbie $RB, $RS", (TLBIEP9 gprc:$RB, gprc:$RS, 0, 0, 0)>;
}

def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
Requires<[IsPPC4xx]>;
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -234,8 +234,8 @@ define dso_local void @P10_Spill_CR_UN(ptr %arg, ptr %arg1, i32 %arg2) local_unn
; CHECK-BE-NEXT: # %bb.4: # %bb37
; CHECK-BE-NEXT: bc 4, 4*cr5+lt, .LBB0_14
; CHECK-BE-NEXT: .LBB0_5: # %bb42
; CHECK-BE-NEXT: addi r3, r3, global_1@toc@l
; CHECK-BE-NEXT: li r4, 0
; CHECK-BE-NEXT: addi r3, r3, global_1@toc@l
; CHECK-BE-NEXT: cmpwi r28, 0
; CHECK-BE-NEXT: isel r3, r3, r4, 4*cr2+gt
; CHECK-BE-NEXT: crnot 4*cr2+lt, eq
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/PowerPC/vector-reduce-add.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1085,14 +1085,14 @@ define dso_local signext i32 @v16i8tov16i32_sign(<16 x i8> %a) local_unnamed_add
; PWR10BE-NEXT: addis r3, r2, .LCPI17_2@toc@ha
; PWR10BE-NEXT: vperm v3, v2, v2, v3
; PWR10BE-NEXT: addi r3, r3, .LCPI17_2@toc@l
; PWR10BE-NEXT: vextsb2w v3, v3
; PWR10BE-NEXT: lxv v5, 0(r3)
; PWR10BE-NEXT: addis r3, r2, .LCPI17_3@toc@ha
; PWR10BE-NEXT: vextsb2w v3, v3
; PWR10BE-NEXT: vperm v4, v2, v2, v4
; PWR10BE-NEXT: addi r3, r3, .LCPI17_3@toc@l
; PWR10BE-NEXT: vextsb2w v4, v4
; PWR10BE-NEXT: lxv v0, 0(r3)
; PWR10BE-NEXT: li r3, 0
; PWR10BE-NEXT: vextsb2w v4, v4
; PWR10BE-NEXT: vperm v5, v2, v2, v5
; PWR10BE-NEXT: vadduwm v3, v4, v3
; PWR10BE-NEXT: vextsb2w v5, v5
Expand Down Expand Up @@ -1212,9 +1212,9 @@ define dso_local zeroext i32 @v16i8tov16i32_zero(<16 x i8> %a) local_unnamed_add
; PWR10BE-NEXT: addis r3, r2, .LCPI18_3@toc@ha
; PWR10BE-NEXT: vperm v5, v4, v2, v5
; PWR10BE-NEXT: addi r3, r3, .LCPI18_3@toc@l
; PWR10BE-NEXT: vadduwm v3, v5, v3
; PWR10BE-NEXT: lxv v1, 0(r3)
; PWR10BE-NEXT: li r3, 0
; PWR10BE-NEXT: vadduwm v3, v5, v3
; PWR10BE-NEXT: vperm v0, v4, v2, v0
; PWR10BE-NEXT: vperm v2, v4, v2, v1
; PWR10BE-NEXT: vadduwm v2, v2, v0
Expand Down Expand Up @@ -1574,36 +1574,36 @@ define dso_local i64 @v16i8tov16i64_sign(<16 x i8> %a) local_unnamed_addr #0 {
; PWR10BE-NEXT: addis r3, r2, .LCPI23_2@toc@ha
; PWR10BE-NEXT: vperm v3, v2, v2, v3
; PWR10BE-NEXT: addi r3, r3, .LCPI23_2@toc@l
; PWR10BE-NEXT: vextsb2d v3, v3
; PWR10BE-NEXT: lxv v5, 0(r3)
; PWR10BE-NEXT: addis r3, r2, .LCPI23_3@toc@ha
; PWR10BE-NEXT: vextsb2d v3, v3
; PWR10BE-NEXT: vperm v4, v2, v2, v4
; PWR10BE-NEXT: addi r3, r3, .LCPI23_3@toc@l
; PWR10BE-NEXT: vextsb2d v4, v4
; PWR10BE-NEXT: lxv v0, 0(r3)
; PWR10BE-NEXT: addis r3, r2, .LCPI23_4@toc@ha
; PWR10BE-NEXT: vextsb2d v4, v4
; PWR10BE-NEXT: vperm v5, v2, v2, v5
; PWR10BE-NEXT: addi r3, r3, .LCPI23_4@toc@l
; PWR10BE-NEXT: vextsb2d v5, v5
; PWR10BE-NEXT: lxv v1, 0(r3)
; PWR10BE-NEXT: addis r3, r2, .LCPI23_5@toc@ha
; PWR10BE-NEXT: vextsb2d v5, v5
; PWR10BE-NEXT: vperm v0, v2, v2, v0
; PWR10BE-NEXT: addi r3, r3, .LCPI23_5@toc@l
; PWR10BE-NEXT: vextsb2d v0, v0
; PWR10BE-NEXT: lxv v6, 0(r3)
; PWR10BE-NEXT: addis r3, r2, .LCPI23_6@toc@ha
; PWR10BE-NEXT: vextsb2d v0, v0
; PWR10BE-NEXT: vperm v1, v2, v2, v1
; PWR10BE-NEXT: addi r3, r3, .LCPI23_6@toc@l
; PWR10BE-NEXT: vaddudm v5, v0, v5
; PWR10BE-NEXT: vaddudm v3, v4, v3
; PWR10BE-NEXT: vaddudm v3, v3, v5
; PWR10BE-NEXT: addi r3, r3, .LCPI23_6@toc@l
; PWR10BE-NEXT: vextsb2d v1, v1
; PWR10BE-NEXT: lxv v7, 0(r3)
; PWR10BE-NEXT: addis r3, r2, .LCPI23_7@toc@ha
; PWR10BE-NEXT: vextsb2d v1, v1
; PWR10BE-NEXT: vperm v6, v2, v2, v6
; PWR10BE-NEXT: addi r3, r3, .LCPI23_7@toc@l
; PWR10BE-NEXT: vextsb2d v6, v6
; PWR10BE-NEXT: lxv v8, 0(r3)
; PWR10BE-NEXT: vextsb2d v6, v6
; PWR10BE-NEXT: vperm v7, v2, v2, v7
; PWR10BE-NEXT: vextsb2d v7, v7
; PWR10BE-NEXT: vperm v2, v2, v2, v8
Expand Down
3 changes: 0 additions & 3 deletions llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -111,9 +111,6 @@
# CHECK: tlbie 4
0x7c 0x00 0x22 0x64

# CHECK: tlbie 4
0x7c 0x00 0x22 0x64

Comment on lines -114 to -116
Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

removing this since it's a duplicate of lines 111-112.

# CHECK: rfi
0x4c 0x00 0x00 0x64
# CHECK: rfci
Expand Down
6 changes: 6 additions & 0 deletions ...mbler/PowerPC/ppc64-encoding-p9vector.txt → ...isassembler/PowerPC/ppc64-encoding-p9.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2,3 +2,9 @@

# CHECK: mtvsrdd 6, 0, 3
0x66 0x1b 0xc0 0x7c

# CHECK: tlbie 8, 10
0x64, 0x42, 0x40, 0x7d

# CHECK: tlbie 8, 10, 2, 1, 0
0x64, 0x42, 0x4a, 0x7d