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[flang][cuda] Add interfaces and lowering for tma_bulk_[commit|wait]_group subroutine #163012

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Merged
merged 1 commit into from
Oct 11, 2025
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[flang][cuda] Add interfaces and lowering for tma_bulk_[commit|wait]_group subroutine #163012

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2 changes: 2 additions & 0 deletions flang/include/flang/Optimizer/Builder/IntrinsicCall.h
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Original file line number Diff line number Diff line change
Expand Up @@ -456,6 +456,8 @@ struct IntrinsicLibrary {
mlir::Value genTand(mlir::Type, llvm::ArrayRef<mlir::Value>);
mlir::Value genTanpi(mlir::Type, llvm::ArrayRef<mlir::Value>);
mlir::Value genTime(mlir::Type, llvm::ArrayRef<mlir::Value>);
void genTMABulkCommitGroup(llvm::ArrayRef<fir::ExtendedValue>);
void genTMABulkWaitGroup(llvm::ArrayRef<fir::ExtendedValue>);
mlir::Value genTrailz(mlir::Type, llvm::ArrayRef<mlir::Value>);
fir::ExtendedValue genTransfer(mlir::Type,
llvm::ArrayRef<fir::ExtendedValue>);
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23 changes: 23 additions & 0 deletions flang/lib/Optimizer/Builder/IntrinsicCall.cpp
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Expand Up @@ -1012,6 +1012,14 @@ static constexpr IntrinsicHandler handlers[]{
{"threadfence_block", &I::genThreadFenceBlock, {}, /*isElemental=*/false},
{"threadfence_system", &I::genThreadFenceSystem, {}, /*isElemental=*/false},
{"time", &I::genTime, {}, /*isElemental=*/false},
{"tma_bulk_commit_group",
&I::genTMABulkCommitGroup,
{{}},
/*isElemental=*/false},
{"tma_bulk_wait_group",
&I::genTMABulkWaitGroup,
{{}},
/*isElemental=*/false},
{"trailz", &I::genTrailz},
{"transfer",
&I::genTransfer,
Expand Down Expand Up @@ -9169,6 +9177,21 @@ mlir::Value IntrinsicLibrary::genTime(mlir::Type resultType,
fir::runtime::genTime(builder, loc));
}

// TMA_BULK_COMMIT_GROUP (CUDA)
void IntrinsicLibrary::genTMABulkCommitGroup(
llvm::ArrayRef<fir::ExtendedValue> args) {
assert(args.size() == 0);
mlir::NVVM::CpAsyncBulkCommitGroupOp::create(builder, loc);
}

// TMA_BULK_WAIT_GROUP (CUDA)
void IntrinsicLibrary::genTMABulkWaitGroup(
llvm::ArrayRef<fir::ExtendedValue> args) {
assert(args.size() == 0);
auto group = builder.getIntegerAttr(builder.getI32Type(), 0);
mlir::NVVM::CpAsyncBulkWaitGroupOp::create(builder, loc, group, {});
}

// TRIM
fir::ExtendedValue
IntrinsicLibrary::genTrim(mlir::Type resultType,
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10 changes: 10 additions & 0 deletions flang/module/cudadevice.f90
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Expand Up @@ -2008,6 +2008,16 @@ attributes(device) function barrier_arrive_cnt(barrier, count) result(token)
end function
end interface

interface
attributes(device) subroutine tma_bulk_commit_group()
end subroutine
end interface

interface
attributes(device) subroutine tma_bulk_wait_group()
end subroutine
end interface

contains

attributes(device) subroutine syncthreads()
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9 changes: 9 additions & 0 deletions flang/test/Lower/CUDA/cuda-device-proc.cuf
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Expand Up @@ -419,3 +419,12 @@ end subroutine
! CHECK: %[[LLVM_PTR:.*]] = fir.convert %[[DECL_SHARED]]#0 : (!fir.ref<i64>) -> !llvm.ptr
! CHECK: %[[SHARED_PTR:.*]] = llvm.addrspacecast %[[LLVM_PTR]] : !llvm.ptr to !llvm.ptr<3>
! CHECK: nvvm.mbarrier.arrive.expect_tx %[[SHARED_PTR]], %{{.*}} : !llvm.ptr<3>, i32

attributes(global) subroutine test_tma()
call tma_bulk_commit_group()
call tma_bulk_wait_group()
end subroutine

! CHECK-LABEL: func.func @_QPtest_tma()
! CHECK: nvvm.cp.async.bulk.commit.group
! CHECK: nvvm.cp.async.bulk.wait_group 0