-
Notifications
You must be signed in to change notification settings - Fork 14.9k
[AArch64] Optimize splat of extending loads to avoid GPR->FPR transfer #163067
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Open
guy-david
wants to merge
1
commit into
main
Choose a base branch
from
users/guy-david/aarch64-dup-zextload
base: main
Could not load branches
Branch not found: {{ refName }}
Loading
Could not load tags
Nothing to show
Loading
Are you sure you want to change the base?
Some commits from the old base branch may be removed from the timeline,
and old review comments may become outdated.
+233
−35
Open
Changes from all commits
Commits
File filter
Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
There are no files selected for viewing
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,139 @@ | ||
| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py | ||
| ; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s | ||
|
|
||
| ; Test optimization of DUP with extended narrow loads | ||
| ; This should avoid GPR->SIMD transfers by loading directly into vector registers | ||
|
|
||
| define <4 x i32> @test_dup_zextload_i8_v4i32(ptr %p) { | ||
| ; CHECK-LABEL: test_dup_zextload_i8_v4i32: | ||
| ; CHECK: // %bb.0: | ||
| ; CHECK-NEXT: ldr b0, [x0] | ||
| ; CHECK-NEXT: dup v0.4s, v0.s[0] | ||
| ; CHECK-NEXT: ret | ||
| %load = load i8, ptr %p, align 1 | ||
| %ext = zext i8 %load to i32 | ||
| %vec = insertelement <4 x i32> poison, i32 %ext, i32 0 | ||
| %dup = shufflevector <4 x i32> %vec, <4 x i32> poison, <4 x i32> zeroinitializer | ||
| ret <4 x i32> %dup | ||
| } | ||
|
|
||
| define <4 x i32> @test_dup_zextload_i16_v4i32(ptr %p) { | ||
| ; CHECK-LABEL: test_dup_zextload_i16_v4i32: | ||
| ; CHECK: // %bb.0: | ||
| ; CHECK-NEXT: ldr h0, [x0] | ||
| ; CHECK-NEXT: dup v0.4s, v0.s[0] | ||
| ; CHECK-NEXT: ret | ||
| %load = load i16, ptr %p, align 2 | ||
| %ext = zext i16 %load to i32 | ||
| %vec = insertelement <4 x i32> poison, i32 %ext, i32 0 | ||
| %dup = shufflevector <4 x i32> %vec, <4 x i32> poison, <4 x i32> zeroinitializer | ||
| ret <4 x i32> %dup | ||
| } | ||
|
|
||
| define <2 x i32> @test_dup_zextload_i8_v2i32(ptr %p) { | ||
| ; CHECK-LABEL: test_dup_zextload_i8_v2i32: | ||
| ; CHECK: // %bb.0: | ||
| ; CHECK-NEXT: ldr b0, [x0] | ||
| ; CHECK-NEXT: dup v0.2s, v0.s[0] | ||
| ; CHECK-NEXT: ret | ||
| %load = load i8, ptr %p, align 1 | ||
| %ext = zext i8 %load to i32 | ||
| %vec = insertelement <2 x i32> poison, i32 %ext, i32 0 | ||
| %dup = shufflevector <2 x i32> %vec, <2 x i32> poison, <2 x i32> zeroinitializer | ||
| ret <2 x i32> %dup | ||
| } | ||
|
|
||
| define <2 x i32> @test_dup_zextload_i16_v2i32(ptr %p) { | ||
| ; CHECK-LABEL: test_dup_zextload_i16_v2i32: | ||
| ; CHECK: // %bb.0: | ||
| ; CHECK-NEXT: ldr h0, [x0] | ||
| ; CHECK-NEXT: dup v0.2s, v0.s[0] | ||
| ; CHECK-NEXT: ret | ||
| %load = load i16, ptr %p, align 2 | ||
| %ext = zext i16 %load to i32 | ||
| %vec = insertelement <2 x i32> poison, i32 %ext, i32 0 | ||
| %dup = shufflevector <2 x i32> %vec, <2 x i32> poison, <2 x i32> zeroinitializer | ||
| ret <2 x i32> %dup | ||
| } | ||
|
|
||
| define <8 x i16> @test_dup_zextload_i8_v8i16(ptr %p) { | ||
| ; CHECK-LABEL: test_dup_zextload_i8_v8i16: | ||
| ; CHECK: // %bb.0: | ||
| ; CHECK-NEXT: ldr b0, [x0] | ||
| ; CHECK-NEXT: dup v0.8h, v0.h[0] | ||
| ; CHECK-NEXT: ret | ||
| %load = load i8, ptr %p, align 1 | ||
| %ext = zext i8 %load to i16 | ||
| %vec = insertelement <8 x i16> poison, i16 %ext, i32 0 | ||
| %dup = shufflevector <8 x i16> %vec, <8 x i16> poison, <8 x i32> zeroinitializer | ||
| ret <8 x i16> %dup | ||
| } | ||
|
|
||
| define <4 x i16> @test_dup_zextload_i8_v4i16(ptr %p) { | ||
| ; CHECK-LABEL: test_dup_zextload_i8_v4i16: | ||
| ; CHECK: // %bb.0: | ||
| ; CHECK-NEXT: ldr b0, [x0] | ||
| ; CHECK-NEXT: dup v0.4h, v0.h[0] | ||
| ; CHECK-NEXT: ret | ||
| %load = load i8, ptr %p, align 1 | ||
| %ext = zext i8 %load to i16 | ||
| %vec = insertelement <4 x i16> poison, i16 %ext, i32 0 | ||
| %dup = shufflevector <4 x i16> %vec, <4 x i16> poison, <4 x i32> zeroinitializer | ||
| ret <4 x i16> %dup | ||
| } | ||
|
|
||
| define <4 x i32> @test_dup_zextload_i8_v4i32_offset(ptr %p) { | ||
| ; CHECK-LABEL: test_dup_zextload_i8_v4i32_offset: | ||
| ; CHECK: // %bb.0: | ||
| ; CHECK-NEXT: ldr b0, [x0, #4] | ||
| ; CHECK-NEXT: dup v0.4s, v0.s[0] | ||
| ; CHECK-NEXT: ret | ||
| %addr = getelementptr inbounds i8, ptr %p, i64 4 | ||
| %load = load i8, ptr %addr, align 1 | ||
| %ext = zext i8 %load to i32 | ||
| %vec = insertelement <4 x i32> poison, i32 %ext, i32 0 | ||
| %dup = shufflevector <4 x i32> %vec, <4 x i32> poison, <4 x i32> zeroinitializer | ||
| ret <4 x i32> %dup | ||
| } | ||
|
|
||
| define <4 x i32> @test_dup_zextload_i16_v4i32_offset(ptr %p) { | ||
| ; CHECK-LABEL: test_dup_zextload_i16_v4i32_offset: | ||
| ; CHECK: // %bb.0: | ||
| ; CHECK-NEXT: ldr h0, [x0, #8] | ||
| ; CHECK-NEXT: dup v0.4s, v0.s[0] | ||
| ; CHECK-NEXT: ret | ||
| %addr = getelementptr inbounds i16, ptr %p, i64 4 | ||
| %load = load i16, ptr %addr, align 2 | ||
| %ext = zext i16 %load to i32 | ||
| %vec = insertelement <4 x i32> poison, i32 %ext, i32 0 | ||
| %dup = shufflevector <4 x i32> %vec, <4 x i32> poison, <4 x i32> zeroinitializer | ||
| ret <4 x i32> %dup | ||
| } | ||
|
|
||
| define <4 x i32> @test_dup_zextload_i8_v4i32_reg_offset(ptr %p, i64 %offset) { | ||
| ; CHECK-LABEL: test_dup_zextload_i8_v4i32_reg_offset: | ||
| ; CHECK: // %bb.0: | ||
| ; CHECK-NEXT: ldr b0, [x0, x1] | ||
| ; CHECK-NEXT: dup v0.4s, v0.s[0] | ||
| ; CHECK-NEXT: ret | ||
| %addr = getelementptr inbounds i8, ptr %p, i64 %offset | ||
| %load = load i8, ptr %addr, align 1 | ||
| %ext = zext i8 %load to i32 | ||
| %vec = insertelement <4 x i32> poison, i32 %ext, i32 0 | ||
| %dup = shufflevector <4 x i32> %vec, <4 x i32> poison, <4 x i32> zeroinitializer | ||
| ret <4 x i32> %dup | ||
| } | ||
|
|
||
| define <4 x i32> @test_dup_zextload_i16_v4i32_reg_offset(ptr %p, i64 %offset) { | ||
| ; CHECK-LABEL: test_dup_zextload_i16_v4i32_reg_offset: | ||
| ; CHECK: // %bb.0: | ||
| ; CHECK-NEXT: ldr h0, [x0, x1, lsl #1] | ||
| ; CHECK-NEXT: dup v0.4s, v0.s[0] | ||
| ; CHECK-NEXT: ret | ||
| %addr = getelementptr inbounds i16, ptr %p, i64 %offset | ||
| %load = load i16, ptr %addr, align 2 | ||
| %ext = zext i16 %load to i32 | ||
| %vec = insertelement <4 x i32> poison, i32 %ext, i32 0 | ||
| %dup = shufflevector <4 x i32> %vec, <4 x i32> poison, <4 x i32> zeroinitializer | ||
| ret <4 x i32> %dup | ||
| } |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Oops, something went wrong.
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
The problem with load patterns is that there are quite a few addressing modes / combinations that we should be supporting but too often do not add patterns for. The combination of all the types gets a bit out of hand. Some patterns should be considered "canonical" though, that we build others on top of.
Is there another basic form of loads we can base these on? If you try and use the extload+bitcast we added lately then those are incomplete (and look wrong to me, I'll make a patch). We could also consider scalar_to_vec(extload) as a base form, if so can you think of a nice templated way to make sure we add all the different addressing forms needed?
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Created a templated form which accepts both
scalar_to_vectorandbitconvertoperations.