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[llvm] Use [[fallthrough]] instead of LLVM_FALLTHROUGH (NFC) #163086

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Merged
merged 1 commit into from
Oct 13, 2025
Merged

[llvm] Use [[fallthrough]] instead of LLVM_FALLTHROUGH (NFC) #163086

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2 changes: 1 addition & 1 deletion llvm/lib/Support/VirtualOutputBackends.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -498,7 +498,7 @@ Error OnDiskOutputFile::keep() {
// Someone else owns the lock on this file, wait.
switch (Lock.waitForUnlockFor(std::chrono::seconds(256))) {
case WaitForUnlockResult::Success:
LLVM_FALLTHROUGH;
[[fallthrough]];
case WaitForUnlockResult::OwnerDied: {
continue; // try again to get the lock.
}
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64Subtarget.cpp
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Expand Up @@ -273,7 +273,7 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) {
EpilogueVectorizationMinVF = 8;
MaxInterleaveFactor = 4;
ScatterOverhead = 13;
LLVM_FALLTHROUGH;
[[fallthrough]];
case NeoverseN2:
case NeoverseN3:
PrefFunctionAlignment = Align(16);
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4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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Expand Up @@ -2356,7 +2356,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32),
AMDGPU::M0)
.add(*TII->getNamedOperand(*MI, AMDGPU::OpName::mask));
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case AMDGPU::SI_SPILL_V1024_SAVE:
case AMDGPU::SI_SPILL_V512_SAVE:
Expand Down Expand Up @@ -2446,7 +2446,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32),
AMDGPU::M0)
.add(*TII->getNamedOperand(*MI, AMDGPU::OpName::mask));
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case AMDGPU::SI_SPILL_V16_RESTORE:
case AMDGPU::SI_SPILL_V32_RESTORE:
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8 changes: 4 additions & 4 deletions llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
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Expand Up @@ -233,7 +233,7 @@ getVectorLoweringShape(EVT VectorEVT, const NVPTXSubtarget &STI,
// target supports 256-bit loads/stores
if (!CanLowerTo256Bit)
return std::nullopt;
LLVM_FALLTHROUGH;
[[fallthrough]];
case MVT::v2i8:
case MVT::v2i64:
case MVT::v2f64:
Expand All @@ -248,7 +248,7 @@ getVectorLoweringShape(EVT VectorEVT, const NVPTXSubtarget &STI,
// global and the target supports 256-bit loads/stores.
if (!CanLowerTo256Bit)
return std::nullopt;
LLVM_FALLTHROUGH;
[[fallthrough]];
case MVT::v2i16: // <1 x i16x2>
case MVT::v2f16: // <1 x f16x2>
case MVT::v2bf16: // <1 x bf16x2>
Expand All @@ -270,7 +270,7 @@ getVectorLoweringShape(EVT VectorEVT, const NVPTXSubtarget &STI,
// target supports 256-bit loads/stores
if (!CanLowerTo256Bit)
return std::nullopt;
LLVM_FALLTHROUGH;
[[fallthrough]];
case MVT::v2f32: // <1 x f32x2>
case MVT::v4f32: // <2 x f32x2>
case MVT::v2i32: // <1 x i32x2>
Expand Down Expand Up @@ -6749,7 +6749,7 @@ NVPTXTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
case AtomicRMWInst::BinOp::Xchg:
if (BitWidth == 128)
return AtomicExpansionKind::None;
LLVM_FALLTHROUGH;
[[fallthrough]];
case AtomicRMWInst::BinOp::And:
case AtomicRMWInst::BinOp::Or:
case AtomicRMWInst::BinOp::Xor:
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
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Expand Up @@ -1688,7 +1688,7 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
(1 << 25) - 1);
// HACK: See comment before `BareSymbolQC_E_LI` in RISCVInstrInfoXqci.td.
case Match_InvalidBareSymbolQC_E_LI:
LLVM_FALLTHROUGH;
[[fallthrough]];
// END HACK
case Match_InvalidBareSImm32:
return generateImmOutOfRangeError(Operands, ErrorInfo,
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16 changes: 8 additions & 8 deletions llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
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Expand Up @@ -84,11 +84,11 @@ bool Xtensa::checkRegister(MCRegister RegNo, const FeatureBitset &FeatureBits,
case Xtensa::CCOMPARE0:
if (FeatureBits[Xtensa::FeatureTimers1])
return true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Xtensa::CCOMPARE1:
if (FeatureBits[Xtensa::FeatureTimers2])
return true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Xtensa::CCOMPARE2:
if (FeatureBits[Xtensa::FeatureTimers3])
return true;
Expand All @@ -107,37 +107,37 @@ bool Xtensa::checkRegister(MCRegister RegNo, const FeatureBitset &FeatureBits,
case Xtensa::EXCSAVE1:
case Xtensa::EXCVADDR:
return FeatureBits[Xtensa::FeatureException];
LLVM_FALLTHROUGH;
[[fallthrough]];
case Xtensa::EPC2:
case Xtensa::EPS2:
case Xtensa::EXCSAVE2:
if (FeatureBits[Xtensa::FeatureHighPriInterrupts])
return true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Xtensa::EPC3:
case Xtensa::EPS3:
case Xtensa::EXCSAVE3:
if (FeatureBits[Xtensa::FeatureHighPriInterruptsLevel3])
return true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Xtensa::EPC4:
case Xtensa::EPS4:
case Xtensa::EXCSAVE4:
if (FeatureBits[Xtensa::FeatureHighPriInterruptsLevel4])
return true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Xtensa::EPC5:
case Xtensa::EPS5:
case Xtensa::EXCSAVE5:
if (FeatureBits[Xtensa::FeatureHighPriInterruptsLevel5])
return true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Xtensa::EPC6:
case Xtensa::EPS6:
case Xtensa::EXCSAVE6:
if (FeatureBits[Xtensa::FeatureHighPriInterruptsLevel6])
return true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Xtensa::EPC7:
case Xtensa::EPS7:
case Xtensa::EXCSAVE7:
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2 changes: 1 addition & 1 deletion llvm/lib/Transforms/ObjCARC/ObjCARCOpts.cpp
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Expand Up @@ -2626,7 +2626,7 @@ void ObjCARCOpt::OptimizeAutoreleasePools(Function &F) {
case ARCInstKind::Call:
if (!MayAutorelease(cast<CallBase>(Inst)))
break;
LLVM_FALLTHROUGH;
[[fallthrough]];
case ARCInstKind::Autorelease:
case ARCInstKind::AutoreleaseRV:
case ARCInstKind::FusedRetainAutorelease:
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
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Expand Up @@ -1154,7 +1154,7 @@ InstructionCost VPInstruction::computeCost(ElementCount VF,
case VPInstruction::ExtractPenultimateElement:
if (VF == ElementCount::getScalable(1))
return InstructionCost::getInvalid();
LLVM_FALLTHROUGH;
[[fallthrough]];
default:
// TODO: Compute cost other VPInstructions once the legacy cost model has
// been retired.
Expand Down Expand Up @@ -2855,7 +2855,7 @@ InstructionCost VPExpressionRecipe::computeCost(ElementCount VF,
case ExpressionTypes::ExtNegatedMulAccReduction:
assert(Opcode == Instruction::Add && "Unexpected opcode");
Opcode = Instruction::Sub;
LLVM_FALLTHROUGH;
[[fallthrough]];
case ExpressionTypes::ExtMulAccReduction: {
return Ctx.TTI.getMulAccReductionCost(
cast<VPWidenCastRecipe>(ExpressionRecipes.front())->getOpcode() ==
Expand Down