Skip to content

[AArch64][llvm] Armv9.7-A: Add support for Memory Partitioning and Management (FEAT_MPAMv2) #163157

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 2 commits into
base: users/jthackray/armv9.7a-feat_tlbid
Choose a base branch
from
Open

[AArch64][llvm] Armv9.7-A: Add support for Memory Partitioning and Management (FEAT_MPAMv2) #163157

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
3bb79bc
[AArch64][llvm] Armv9.7-A: Add support for Memory Partitioning and Ma…
jthackray Sep 8, 2025
798d159
fixup! [AArch64][llvm] Armv9.7-A: Add support for Memory Partitioning…
jthackray Oct 13, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 4 additions & 0 deletions clang/test/Driver/aarch64-v97a.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -29,3 +29,7 @@
// RUN: %clang -target aarch64 -march=armv9.7a+tlbid -### -c %s 2>&1 | FileCheck -check-prefix=V97A-TLBID %s
// RUN: %clang -target aarch64 -march=armv9.7-a+tlbid -### -c %s 2>&1 | FileCheck -check-prefix=V97A-TLBID %s
// V97A-TLBID: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+tlbid"

// RUN: %clang -target aarch64 -march=armv9.7a+mpamv2 -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MPAMv2 %s
// RUN: %clang -target aarch64 -march=armv9.7-a+mpamv2 -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MPAMv2 %s
// V97A-MPAMv2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+mpamv2"
1 change: 1 addition & 0 deletions clang/test/Driver/print-supported-extensions-aarch64.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -45,6 +45,7 @@
// CHECK-NEXT: lsui FEAT_LSUI Enable Armv9.6-A unprivileged load/store instructions
// CHECK-NEXT: lut FEAT_LUT Enable Lookup Table instructions
// CHECK-NEXT: mops FEAT_MOPS Enable Armv8.8-A memcpy and memset acceleration instructions
// CHECK-NEXT: mpamv2 FEAT_MPAMv2 Enable Armv9.7-A MPAMv2 Lookaside Buffer Invalidate instructions
// CHECK-NEXT: memtag FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
// CHECK-NEXT: simd FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: occmo FEAT_OCCMO Enable Armv9.6-A Outer cacheable cache maintenance operations
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/AArch64/AArch64Features.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -598,6 +598,9 @@ def FeatureLSCP : ExtensionWithMArch<"lscp", "LSCP", "FEAT_LSCP",
def FeatureTLBID: ExtensionWithMArch<"tlbid", "TLBID", "FEAT_TLBID",
"Enable Armv9.7-A TLBI Domains extension">;

def FeatureMPAMv2: ExtensionWithMArch<"mpamv2", "MPAMv2", "FEAT_MPAMv2",
"Enable Armv9.7-A MPAMv2 Lookaside Buffer Invalidate instructions">;

//===----------------------------------------------------------------------===//
// Other Features
//===----------------------------------------------------------------------===//
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -402,6 +402,8 @@ def HasCPA : Predicate<"Subtarget->hasCPA()">,
AssemblerPredicateWithAll<(all_of FeatureCPA), "cpa">;
def HasTLBID : Predicate<"Subtarget->hasTLBID()">,
AssemblerPredicateWithAll<(all_of FeatureTLBID), "tlbid">;
def HasMPAMv2 : Predicate<"Subtarget->hasMPAMv2()">,
AssemblerPredicateWithAll<(all_of FeatureMPAMv2), "mpamv2">;
def IsLE : Predicate<"Subtarget->isLittleEndian()">;
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
def IsWindows : Predicate<"Subtarget->isTargetWindows()">;
Expand Down
59 changes: 52 additions & 7 deletions llvm/lib/Target/AArch64/AArch64SystemOperands.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1880,12 +1880,6 @@ def : ROSysReg<"ERXPFGF_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b100>;
// v8.4a MPAM registers
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureMPAM} }] in {
def : RWSysReg<"MPAM0_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b001>;
def : RWSysReg<"MPAM1_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b000>;
def : RWSysReg<"MPAM2_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b000>;
def : RWSysReg<"MPAM3_EL3", 0b11, 0b110, 0b1010, 0b0101, 0b000>;
def : RWSysReg<"MPAM1_EL12", 0b11, 0b101, 0b1010, 0b0101, 0b000>;
def : RWSysReg<"MPAMHCR_EL2", 0b11, 0b100, 0b1010, 0b0100, 0b000>;
def : RWSysReg<"MPAMVPMV_EL2", 0b11, 0b100, 0b1010, 0b0100, 0b001>;
def : RWSysReg<"MPAMVPM0_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b000>;
def : RWSysReg<"MPAMVPM1_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b001>;
Expand All @@ -1895,7 +1889,6 @@ def : RWSysReg<"MPAMVPM4_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b100>;
def : RWSysReg<"MPAMVPM5_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b101>;
def : RWSysReg<"MPAMVPM6_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b110>;
def : RWSysReg<"MPAMVPM7_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b111>;
def : ROSysReg<"MPAMIDR_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b100>;
} //FeatureMPAM

// v8.4a Activity Monitor registers
Expand Down Expand Up @@ -2336,6 +2329,26 @@ def : RWSysReg<"MPAMBW0_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b101>;
def : RWSysReg<"MPAMBWCAP_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b110>;
def : RWSysReg<"MPAMBWSM_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b111>;

// v9.7a Memory partitioning and monitoring version 2
// (FEAT_MPAMv2) registers
// Op0 Op1 CRn CRm Op2
// MPAM system registers that are also available for MPAMv2
def : RWSysReg<"MPAM0_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b001>;
def : RWSysReg<"MPAM1_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b000>;
def : RWSysReg<"MPAM1_EL12", 0b11, 0b101, 0b1010, 0b0101, 0b000>;
def : RWSysReg<"MPAM2_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b000>;
def : RWSysReg<"MPAM3_EL3", 0b11, 0b110, 0b1010, 0b0101, 0b000>;
def : RWSysReg<"MPAMHCR_EL2", 0b11, 0b100, 0b1010, 0b0100, 0b000>;
def : ROSysReg<"MPAMIDR_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b100>;
// Only MPAMv2 registers
def : RWSysReg<"MPAMCTL_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b010>;
def : RWSysReg<"MPAMCTL_EL12", 0b11, 0b101, 0b1010, 0b0101, 0b010>;
def : RWSysReg<"MPAMCTL_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b010>;
def : RWSysReg<"MPAMCTL_EL3", 0b11, 0b110, 0b1010, 0b0101, 0b010>;
def : RWSysReg<"MPAMVIDCR_EL2", 0b11, 0b100, 0b1010, 0b0111, 0b000>;
def : RWSysReg<"MPAMVIDSR_EL2", 0b11, 0b100, 0b1010, 0b0111, 0b001>;
def : RWSysReg<"MPAMVIDSR_EL3", 0b11, 0b110, 0b1010, 0b0111, 0b001>;

//===----------------------------------------------------------------------===//
// FEAT_SRMASK v9.6a registers
//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -2429,3 +2442,35 @@ def : DC<"CIVAPS", 0b000, 0b0111, 0b1111, 0b001>;
let Requires = [{ {AArch64::FeaturePoPS, AArch64::FeatureMTE} }] in {
def : DC<"CIGDVAPS", 0b000, 0b0111, 0b1111, 0b101>;
}

// MPAM Lookaside Buffer Invalidate (MLBI) instructions
class MLBI<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2, bit needsreg> {
string Name = name;
bits<14> Encoding;
let Encoding{13-11} = op1;
let Encoding{10-7} = crn;
let Encoding{6-3} = crm;
let Encoding{2-0} = op2;
bit NeedsReg = needsreg;
string RequiresStr = [{ {AArch64::FeatureMPAMv2} }];
}

def MLBITable : GenericTable {
let FilterClass = "MLBI";
let CppTypeName = "MLBI";
let Fields = ["Name", "Encoding", "NeedsReg", "RequiresStr"];

let PrimaryKey = ["Encoding"];
let PrimaryKeyName = "lookupMLBIByEncoding";
}

def lookupMLBIByName : SearchIndex {
let Table = MLBITable;
let Key = ["Name"];
}

// Op1 CRn CRm Op2 needsReg
def : MLBI<"ALLE1", 0b100, 0b0111, 0b0000, 0b100, 0>;
def : MLBI<"VMALLE1", 0b100, 0b0111, 0b0000, 0b101, 0>;
def : MLBI<"VPIDE1", 0b100, 0b0111, 0b0000, 0b110, 1>;
def : MLBI<"VPMGE1", 0b100, 0b0111, 0b0000, 0b111, 1>;
27 changes: 21 additions & 6 deletions llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3886,6 +3886,7 @@ static const struct Extension {
{"cmh", {AArch64::FeatureCMH}},
{"lscp", {AArch64::FeatureLSCP}},
{"tlbid", {AArch64::FeatureTLBID}},
{"mpamv2", {AArch64::FeatureMPAMv2}},
};

static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
Expand Down Expand Up @@ -3958,8 +3959,9 @@ void AArch64AsmParser::createSysAlias(uint16_t Encoding, OperandVector &Operands
AArch64Operand::CreateImm(Expr, S, getLoc(), getContext()));
}

/// parseSysAlias - The IC, DC, AT, and TLBI instructions are simple aliases for
/// the SYS instruction. Parse them specially so that we create a SYS MCInst.
/// parseSysAlias - The IC, DC, AT, TLBI, and MLBI instructions
/// are simple aliases for the SYS instruction. Parse them specially so that
/// we create a SYS MCInst.
bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
OperandVector &Operands) {
if (Name.contains('.'))
Expand Down Expand Up @@ -4021,7 +4023,19 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
OptionalRegister = TLBI->OptionalReg;
}
createSysAlias(TLBI->Encoding, Operands, S);
} else if (Mnemonic == "cfp" || Mnemonic == "dvp" || Mnemonic == "cpp" || Mnemonic == "cosp") {
} else if (Mnemonic == "mlbi") {
const AArch64MLBI::MLBI *MLBI = AArch64MLBI::lookupMLBIByName(Op);
if (!MLBI)
return TokError("invalid operand for MLBI instruction");
else if (!MLBI->haveFeatures(getSTI().getFeatureBits())) {
std::string Str("MLBI " + std::string(MLBI->Name) + " requires: ");
setRequiredFeatureString(MLBI->getRequiredFeatures(), Str);
return TokError(Str);
}
ExpectRegister = MLBI->NeedsReg;
createSysAlias(MLBI->Encoding, Operands, S);
} else if (Mnemonic == "cfp" || Mnemonic == "dvp" || Mnemonic == "cpp" ||
Mnemonic == "cosp") {

if (Op.lower() != "rctx")
return TokError("invalid operand for prediction restriction instruction");
Expand Down Expand Up @@ -5338,10 +5352,11 @@ bool AArch64AsmParser::parseInstruction(ParseInstructionInfo &Info,
size_t Start = 0, Next = Name.find('.');
StringRef Head = Name.slice(Start, Next);

// IC, DC, AT, TLBI and Prediction invalidation instructions are aliases for
// the SYS instruction.
// IC, DC, AT, TLBI, MLBI and Prediction invalidation instructions are aliases
// for the SYS instruction.
if (Head == "ic" || Head == "dc" || Head == "at" || Head == "tlbi" ||
Head == "cfp" || Head == "dvp" || Head == "cpp" || Head == "cosp")
Head == "cfp" || Head == "dvp" || Head == "cpp" || Head == "cosp" ||
Head == "mlbi")
return parseSysAlias(Head, NameLoc, Operands);

// TLBIP instructions are aliases for the SYSP instruction.
Expand Down
11 changes: 11 additions & 0 deletions llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -917,6 +917,17 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
if (CnVal == 7) {
switch (CmVal) {
default: return false;
// MLBI aliases
case 0: {
const AArch64MLBI::MLBI *MLBI =
AArch64MLBI::lookupMLBIByEncoding(Encoding);
if (!MLBI || !MLBI->haveFeatures(STI.getFeatureBits()))
return false;

NeedsReg = MLBI->NeedsReg;
Ins = "mlbi\t";
Name = std::string(MLBI->Name);
} break;
// Maybe IC, maybe Prediction Restriction
case 1:
switch (Op1Val) {
Expand Down
5 changes: 5 additions & 0 deletions llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -197,6 +197,11 @@ namespace AArch64TLBIP {
#define GET_TLBIPTable_IMPL
#include "AArch64GenSystemOperands.inc"
} // namespace AArch64TLBIP

namespace AArch64MLBI {
#define GET_MLBITable_IMPL
#include "AArch64GenSystemOperands.inc"
} // namespace AArch64MLBI
} // namespace llvm

namespace llvm {
Expand Down
8 changes: 8 additions & 0 deletions llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -821,6 +821,14 @@ struct TLBIP : SysAliasOptionalReg {
#include "AArch64GenSystemOperands.inc"
} // namespace AArch64TLBIP

namespace AArch64MLBI {
struct MLBI : SysAliasReg {
using SysAliasReg::SysAliasReg;
};
#define GET_MLBITable_DECL
#include "AArch64GenSystemOperands.inc"
} // namespace AArch64MLBI

namespace AArch64II {
/// Target Operand Flag enum.
enum TOF {
Expand Down
48 changes: 2 additions & 46 deletions llvm/test/MC/AArch64/armv8.4a-mpam.s
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,5 +1,4 @@
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s 2> %t | FileCheck %s --check-prefix=CHECK
// RUN: FileCheck --check-prefix=CHECK-RO < %t %s
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR

//------------------------------------------------------------------------------
Expand Down Expand Up @@ -56,9 +55,6 @@ mrs x0, MPAMIDR_EL1
//CHECK: msr MPAMVPM6_EL2, x0 // encoding: [0xc0,0xa6,0x1c,0xd5]
//CHECK: msr MPAMVPM7_EL2, x0 // encoding: [0xe0,0xa6,0x1c,0xd5]

//CHECK-RO: error: expected writable system register or pstate
//CHECK-RO: msr MPAMIDR_EL1, x0
//CHECK-RO: ^

//CHECK: mrs x0, MPAM0_EL1 // encoding: [0x20,0xa5,0x38,0xd5]
//CHECK: mrs x0, MPAM1_EL1 // encoding: [0x00,0xa5,0x38,0xd5]
Expand All @@ -77,24 +73,7 @@ mrs x0, MPAMIDR_EL1
//CHECK: mrs x0, MPAMVPM7_EL2 // encoding: [0xe0,0xa6,0x3c,0xd5]
//CHECK: mrs x0, MPAMIDR_EL1 // encoding: [0x80,0xa4,0x38,0xd5]

//CHECK-ERROR: error: expected writable system register or pstate
//CHECK-ERROR: msr MPAM0_EL1, x0
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected writable system register or pstate
//CHECK-ERROR: msr MPAM1_EL1, x0
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected writable system register or pstate
//CHECK-ERROR: msr MPAM2_EL2, x0
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected writable system register or pstate
//CHECK-ERROR: msr MPAM3_EL3, x0
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected writable system register or pstate
//CHECK-ERROR: msr MPAM1_EL12, x0
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected writable system register or pstate
//CHECK-ERROR: msr MPAMHCR_EL2, x0
//CHECK-ERROR: ^

//CHECK-ERROR: error: expected writable system register or pstate
//CHECK-ERROR: msr MPAMVPMV_EL2, x0
//CHECK-ERROR: ^
Expand Down Expand Up @@ -122,28 +101,8 @@ mrs x0, MPAMIDR_EL1
//CHECK-ERROR: error: expected writable system register or pstate
//CHECK-ERROR: msr MPAMVPM7_EL2, x0
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected writable system register or pstate
//CHECK-ERROR: msr MPAMIDR_EL1, x0
//CHECK-ERROR: ^

//CHECK-ERROR: error: expected readable system register
//CHECK-ERROR: mrs x0, MPAM0_EL1
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected readable system register
//CHECK-ERROR: mrs x0, MPAM1_EL1
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected readable system register
//CHECK-ERROR: mrs x0, MPAM2_EL2
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected readable system register
//CHECK-ERROR: mrs x0, MPAM3_EL3
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected readable system register
//CHECK-ERROR: mrs x0, MPAM1_EL12
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected readable system register
//CHECK-ERROR: mrs x0, MPAMHCR_EL2
//CHECK-ERROR: ^

//CHECK-ERROR: error: expected readable system register
//CHECK-ERROR: mrs x0, MPAMVPMV_EL2
//CHECK-ERROR: ^
Expand Down Expand Up @@ -171,6 +130,3 @@ mrs x0, MPAMIDR_EL1
//CHECK-ERROR: error: expected readable system register
//CHECK-ERROR: mrs x0, MPAMVPM7_EL2
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected readable system register
//CHECK-ERROR: mrs x0, MPAMIDR_EL1
//CHECK-ERROR: ^
9 changes: 9 additions & 0 deletions llvm/test/MC/AArch64/armv9.7a-mpamv2-diagnostics.s
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,9 @@
// RUN: not llvm-mc -triple=aarch64 -mattr=+mpamv2 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR

//------------------------------------------------------------------------------
// Armv9.7-A FEAT_MPAMV2 Extensions
//------------------------------------------------------------------------------

mlbi alle1, x30
// CHECK-ERROR: error: specified mlbi op does not use a register
Loading