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[AArch64][llvm] Armv9.7-A: Add support for Virtual Memory Tagging (FEAT_MTETC) #163158

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[AArch64][llvm] Armv9.7-A: Add support for Virtual Memory Tagging (FEAT_MTETC) #163158

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e875238
[AArch64][llvm] Armv9.7-A: Add support for Virtual Memory Tagging (FE…
jthackray Sep 5, 2025
bafe3fc
fixup! [AArch64][llvm] Armv9.7-A: Add support for Virtual Memory Tagg…
jthackray Oct 13, 2025
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4 changes: 4 additions & 0 deletions clang/test/Driver/aarch64-v97a.c
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Expand Up @@ -33,3 +33,7 @@
// RUN: %clang -target aarch64 -march=armv9.7a+mpamv2 -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MPAMv2 %s
// RUN: %clang -target aarch64 -march=armv9.7-a+mpamv2 -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MPAMv2 %s
// V97A-MPAMv2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+mpamv2"

// RUN: %clang -target aarch64 -march=armv9.7a+mtetc -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MTETC %s
// RUN: %clang -target aarch64 -march=armv9.7-a+mtetc -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MTETC %s
// V97A-MTETC: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+mtetc"
1 change: 1 addition & 0 deletions clang/test/Driver/print-supported-extensions-aarch64.c
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Expand Up @@ -47,6 +47,7 @@
// CHECK-NEXT: mops FEAT_MOPS Enable Armv8.8-A memcpy and memset acceleration instructions
// CHECK-NEXT: mpamv2 FEAT_MPAMv2 Enable Armv9.7-A MPAMv2 Lookaside Buffer Invalidate instructions
// CHECK-NEXT: memtag FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
// CHECK-NEXT: mtetc FEAT_MTETC Enable Virtual Memory Tagging Extension
// CHECK-NEXT: simd FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: occmo FEAT_OCCMO Enable Armv9.6-A Outer cacheable cache maintenance operations
// CHECK-NEXT: pauth FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
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3 changes: 3 additions & 0 deletions llvm/lib/Target/AArch64/AArch64Features.td
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Expand Up @@ -601,6 +601,9 @@ def FeatureTLBID: ExtensionWithMArch<"tlbid", "TLBID", "FEAT_TLBID",
def FeatureMPAMv2: ExtensionWithMArch<"mpamv2", "MPAMv2", "FEAT_MPAMv2",
"Enable Armv9.7-A MPAMv2 Lookaside Buffer Invalidate instructions">;

def FeatureMTETC: ExtensionWithMArch<"mtetc", "MTETC", "FEAT_MTETC",
"Enable Virtual Memory Tagging Extension">;

//===----------------------------------------------------------------------===//
// Other Features
//===----------------------------------------------------------------------===//
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2 changes: 2 additions & 0 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.td
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Expand Up @@ -404,6 +404,8 @@ def HasTLBID : Predicate<"Subtarget->hasTLBID()">,
AssemblerPredicateWithAll<(all_of FeatureTLBID), "tlbid">;
def HasMPAMv2 : Predicate<"Subtarget->hasMPAMv2()">,
AssemblerPredicateWithAll<(all_of FeatureMPAMv2), "mpamv2">;
def HasMTETC : Predicate<"Subtarget->hasMTETC()">,
AssemblerPredicateWithAll<(all_of FeatureMTETC), "mtetc">;
def IsLE : Predicate<"Subtarget->isLittleEndian()">;
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
def IsWindows : Predicate<"Subtarget->isTargetWindows()">;
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6 changes: 6 additions & 0 deletions llvm/lib/Target/AArch64/AArch64SystemOperands.td
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Expand Up @@ -205,6 +205,7 @@ def lookupDCByName : SearchIndex {
let Key = ["Name"];
}

// Op1 CRn CRm Op2
def : DC<"ZVA", 0b011, 0b0111, 0b0100, 0b001>;
def : DC<"IVAC", 0b000, 0b0111, 0b0110, 0b001>;
def : DC<"ISW", 0b000, 0b0111, 0b0110, 0b010>;
Expand Down Expand Up @@ -241,6 +242,11 @@ def : DC<"CIGDVAC", 0b011, 0b0111, 0b1110, 0b101>;
def : DC<"GZVA", 0b011, 0b0111, 0b0100, 0b100>;
}

let Requires = [{ {AArch64::FeatureMTETC} }] in {
def : DC<"ZGBVA", 0b011, 0b0111, 0b0100, 0b101>;
def : DC<"GBVA", 0b011, 0b0111, 0b0100, 0b111>;
}

let Requires = [{ {AArch64::FeatureMEC} }] in {
def : DC<"CIPAE", 0b100, 0b0111, 0b1110, 0b000>;
def : DC<"CIGDPAE", 0b100, 0b0111, 0b1110, 0b111>;
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1 change: 1 addition & 0 deletions llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
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Expand Up @@ -3887,6 +3887,7 @@ static const struct Extension {
{"lscp", {AArch64::FeatureLSCP}},
{"tlbid", {AArch64::FeatureTLBID}},
{"mpamv2", {AArch64::FeatureMPAMv2}},
{"mtetc", {AArch64::FeatureMTETC}},
};

static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
Expand Down
29 changes: 29 additions & 0 deletions llvm/test/MC/AArch64/arm-mtetc.s
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@@ -0,0 +1,29 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mtetc < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+all < %s \
// RUN: | llvm-objdump -d --mattr=+mtetc --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+all < %s \
// RUN: | llvm-objdump -d --mattr=-mtetc --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mtetc < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+mtetc -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST

//------------------------------------------------------------------------------
// FEAT_MTETC Extension instructions
//------------------------------------------------------------------------------

dc zgbva, x0
// CHECK-INST: dc zgbva, x0
// CHECK-ENCODING: [0xa0,0x74,0x0b,0xd5]
// CHECK-UNKNOWN: d50b74a0 sys #3, c7, c4, #5, x0
// CHECK-ERROR: DC ZGBVA requires: mtetc

dc gbva, x0
// CHECK-INST: dc gbva, x0
// CHECK-ENCODING: [0xe0,0x74,0x0b,0xd5]
// CHECK-UNKNOWN: d50b74e0 sys #3, c7, c4, #7, x0
// CHECK-ERROR: DC GBVA requires: mtetc
4 changes: 3 additions & 1 deletion llvm/unittests/TargetParser/TargetParserTest.cpp
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Expand Up @@ -1445,7 +1445,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_SSVE_BITPERM, AArch64::AEK_SVESHA3,
AArch64::AEK_SVESM4, AArch64::AEK_CMH,
AArch64::AEK_LSCP, AArch64::AEK_TLBID,
AArch64::AEK_MPAMV2,
AArch64::AEK_MPAMV2, AArch64::AEK_MTETC,
};

std::vector<StringRef> Features;
Expand Down Expand Up @@ -1561,6 +1561,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
EXPECT_TRUE(llvm::is_contained(Features, "+lscp"));
EXPECT_TRUE(llvm::is_contained(Features, "+tlbid"));
EXPECT_TRUE(llvm::is_contained(Features, "+mpamv2"));
EXPECT_TRUE(llvm::is_contained(Features, "+mtetc"));

// Assuming we listed every extension above, this should produce the same
// result.
Expand Down Expand Up @@ -1731,6 +1732,7 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
{"lscp", "nolscp", "+lscp", "-lscp"},
{"tlbid", "notlbid", "+tlbid", "-tlbid"},
{"mpamv2", "nompamv2", "+mpamv2", "-mpamv2"},
{"mtetc", "nomtetc", "+mtetc", "-mtetc"},
};

for (unsigned i = 0; i < std::size(ArchExt); i++) {
Expand Down