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[SLP]Enable Sub as a base instruction in copyables #163231

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[SLP]Enable Sub as a base instruction in copyables #163231

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d405138
[𝘀𝗽𝗿] initial version
alexey-bataev Oct 13, 2025
e38cd11
Rebase, address comments
alexey-bataev Oct 17, 2025
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24 changes: 15 additions & 9 deletions llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -10657,10 +10657,11 @@ class InstructionsCompatibilityAnalysis {
/// Checks if the opcode is supported as the main opcode for copyable
/// elements.
static bool isSupportedOpcode(const unsigned Opcode) {
return Opcode == Instruction::Add || Opcode == Instruction::LShr ||
Opcode == Instruction::Shl || Opcode == Instruction::SDiv ||
Opcode == Instruction::UDiv || Opcode == Instruction::And ||
Opcode == Instruction::Or || Opcode == Instruction::Xor;
return Opcode == Instruction::Add || Opcode == Instruction::Sub ||
Opcode == Instruction::LShr || Opcode == Instruction::Shl ||
Opcode == Instruction::SDiv || Opcode == Instruction::UDiv ||
Opcode == Instruction::And || Opcode == Instruction::Or ||
Opcode == Instruction::Xor;
}

/// Identifies the best candidate value, which represents main opcode
Expand All @@ -10678,7 +10679,7 @@ class InstructionsCompatibilityAnalysis {
};
// Exclude operands instructions immediately to improve compile time, it
// will be unable to schedule anyway.
SmallDenseSet<Value *, 8> Operands;
SmallDenseMap<unsigned, SmallDenseSet<Value *, 8>> Operands;
SmallMapVector<unsigned, SmallVector<Instruction *>, 4> Candidates;
bool AnyUndef = false;
for (Value *V : VL) {
Expand All @@ -10692,12 +10693,12 @@ class InstructionsCompatibilityAnalysis {
if (Candidates.empty()) {
Candidates.try_emplace(I->getOpcode()).first->second.push_back(I);
Parent = I->getParent();
Operands.insert(I->op_begin(), I->op_end());
Operands[I->getOpcode()].insert(I->op_begin(), I->op_end());
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Why are you now having to filter by opcode?

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After some thoughts and testing restored original

continue;
}
if (Parent == I->getParent()) {
Candidates.try_emplace(I->getOpcode()).first->second.push_back(I);
Operands.insert(I->op_begin(), I->op_end());
Operands[I->getOpcode()].insert(I->op_begin(), I->op_end());
continue;
}
auto *NodeA = DT.getNode(Parent);
Expand All @@ -10712,16 +10713,20 @@ class InstructionsCompatibilityAnalysis {
Candidates.try_emplace(I->getOpcode()).first->second.push_back(I);
Parent = I->getParent();
Operands.clear();
Operands.insert(I->op_begin(), I->op_end());
Operands[I->getOpcode()].insert(I->op_begin(), I->op_end());
}
}
unsigned BestOpcodeNum = 0;
MainOp = nullptr;
for (const auto &P : Candidates) {
if (P.second.size() < BestOpcodeNum)
continue;
const auto &Ops = Operands.at(P.first);
// If have inner dependencies - skip.
if (any_of(P.second, [&](Instruction *I) { return Ops.contains(I); }))
continue;
for (Instruction *I : P.second) {
if (IsSupportedInstruction(I, AnyUndef) && !Operands.contains(I)) {
if (IsSupportedInstruction(I, AnyUndef)) {
MainOp = I;
BestOpcodeNum = P.second.size();
break;
Expand Down Expand Up @@ -10981,6 +10986,7 @@ class InstructionsCompatibilityAnalysis {
getWidenedType(S.getMainOp()->getType(), VL.size());
switch (MainOpcode) {
case Instruction::Add:
case Instruction::Sub:
case Instruction::LShr:
case Instruction::Shl:
case Instruction::SDiv:
Expand Down
11 changes: 2 additions & 9 deletions llvm/test/Transforms/SLPVectorizer/X86/minbw-node-used-twice.ll
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Expand Up @@ -4,15 +4,8 @@
define i8 @test() {
; CHECK-LABEL: define i8 @test() {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[SUB_I_I79_PEEL_I:%.*]] = sub i16 0, 1
; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i16> <i16 poison, i16 0>, i16 [[SUB_I_I79_PEEL_I]], i32 0
; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i16> [[TMP0]] to <2 x i32>
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <2 x i32> zeroinitializer, [[TMP2]]
; CHECK-NEXT: [[TMP3:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i16>
; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i16> [[TMP3]], [[TMP0]]
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq <2 x i16> [[TMP4]], [[TMP0]]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i1> [[TMP1]], i32 0
; CHECK-NEXT: [[CONV13_I89_PEEL_I:%.*]] = zext i1 [[TMP5]] to i8
; CHECK-NEXT: [[TMP0:%.*]] = icmp eq <2 x i16> <i16 -1, i16 0>, <i16 -1, i16 0>
; CHECK-NEXT: [[CONV13_I89_PEEL_I:%.*]] = zext i1 false to i8
; CHECK-NEXT: ret i8 [[CONV13_I89_PEEL_I]]
;
entry:
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/Transforms/SLPVectorizer/X86/parent-node-non-schedulable.ll
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Expand Up @@ -6,12 +6,12 @@ define void @test(ptr %0, i64 %1, i64 %2, i1 %3, i64 %4, i64 %5) {
; CHECK-SAME: ptr [[TMP0:%.*]], i64 [[TMP1:%.*]], i64 [[TMP2:%.*]], i1 [[TMP3:%.*]], i64 [[TMP4:%.*]], i64 [[TMP5:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 240
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 128
; CHECK-NEXT: [[TMP13:%.*]] = load <2 x i64>, ptr [[TMP7]], align 4
; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr null, align 4
; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i64> poison, i64 [[TMP1]], i32 0
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x i64> [[TMP9]], <4 x i64> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i64> <i64 1, i64 1, i64 1, i64 poison>, i64 [[TMP2]], i32 3
; CHECK-NEXT: [[TMP12:%.*]] = add <4 x i64> [[TMP10]], [[TMP11]]
; CHECK-NEXT: [[TMP13:%.*]] = load <2 x i64>, ptr [[TMP7]], align 4
; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr null, align 4
; CHECK-NEXT: [[TMP15:%.*]] = load <2 x i64>, ptr [[TMP8]], align 4
; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <2 x i64> [[TMP13]], <2 x i64> [[TMP15]], <6 x i32> <i32 0, i32 1, i32 poison, i32 3, i32 2, i32 2>
; CHECK-NEXT: [[TMP17:%.*]] = insertelement <6 x i64> poison, i64 [[TMP14]], i32 0
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
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Expand Up @@ -183,7 +183,7 @@ define void @addsub1(ptr noalias %dst, ptr noalias %src) {
; CHECK-LABEL: @addsub1(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[SRC:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = add nsw <4 x i32> [[TMP0]], <i32 -1, i32 1, i32 0, i32 3>
; CHECK-NEXT: [[TMP1:%.*]] = sub nsw <4 x i32> [[TMP0]], <i32 1, i32 -1, i32 0, i32 -3>
; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr [[DST:%.*]], align 4
; CHECK-NEXT: ret void
;
Expand Down