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[AMDGPU] Enable saving SHARED_BASE to VCC #163244

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Merged
merged 2 commits into from
Oct 13, 2025
Merged

[AMDGPU] Enable saving SHARED_BASE to VCC #163244

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0a1f745
Enable saving SHARED_BASE to VCC.
carlobertolli Oct 13, 2025
06ca679
Update llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
carlobertolli Oct 13, 2025
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3 changes: 2 additions & 1 deletion llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -899,7 +899,8 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
}

if (DestReg == AMDGPU::VCC) {
if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
if (AMDGPU::SReg_64RegClass.contains(SrcReg) ||
AMDGPU::SReg_64_EncodableRegClass.contains(SrcReg)) {
BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
.addReg(SrcReg, getKillRegState(KillSrc));
} else {
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9 changes: 9 additions & 0 deletions llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
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Expand Up @@ -58,6 +58,15 @@ body: |
$sgpr0_sgpr1 = COPY $src_shared_base
...

---
name: src_shared_base_to_vcc
body: |
bb.0:
; GFX9-LABEL: name: src_shared_base_to_vcc
; GFX9: $vcc = S_MOV_B64 $src_shared_base
$vcc = COPY $src_shared_base
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@arsenm arsenm Oct 13, 2025

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Also test the inverse case?

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@arsenm arsenm Oct 18, 2025

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ping. We do not structurally prevent writing to constant registers and it is encodable

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@carlobertolli carlobertolli Oct 19, 2025 •
edited
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@arsenm I added a test to copy vcc to shared_base but it fails

name: vcc_to_src_shared_base
body: |
bb.0:
; GFX9-LABEL: name: vcc_to_src_shared_base
; GFX9: $src_shared_base = S_MOV_B64 $vcc
$src_shared_base = COPY $vcc
...

I';ll have to fix the copy to enable this, unless I misunderstood you?

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@carlobertolli carlobertolli Oct 19, 2025

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like this?
#164138

...

---
name: sgpr96_aligned_src_dst
body: |
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