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[sroa][profcheck] Propagate select profile #163317

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Merged
mtrofin merged 1 commit into from
Oct 14, 2025
Merged

[sroa][profcheck] Propagate select profile #163317

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2 changes: 1 addition & 1 deletion llvm/lib/Transforms/Scalar/SROA.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1777,7 +1777,7 @@ static void speculateSelectInstLoads(SelectInst &SI, LoadInst &LI,
}

Value *V = IRB.CreateSelect(SI.getCondition(), TL, FL,
LI.getName() + ".sroa.speculated");
LI.getName() + ".sroa.speculated", &SI);

LLVM_DEBUG(dbgs() << " speculated to: " << *V << "\n");
LI.replaceAllUsesWith(V);
Expand Down
22 changes: 18 additions & 4 deletions llvm/test/Transforms/SROA/phi-and-select.ll
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals
; RUN: opt < %s -passes='sroa<preserve-cfg>' -S | FileCheck %s --check-prefixes=CHECK,CHECK-PRESERVE-CFG
; RUN: opt < %s -passes='sroa<modify-cfg>' -S | FileCheck %s --check-prefixes=CHECK,CHECK-MODIFY-CFG
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
Expand Down Expand Up @@ -36,11 +36,11 @@ exit:
ret i32 %result
}

define i32 @test2() {
define i32 @test2() !prof !0 {
; CHECK-LABEL: @test2(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[COND:%.*]] = icmp sle i32 0, 1
; CHECK-NEXT: [[RESULT_SROA_SPECULATED:%.*]] = select i1 [[COND]], i32 1, i32 0
; CHECK-NEXT: [[RESULT_SROA_SPECULATED:%.*]] = select i1 [[COND]], i32 1, i32 0, !prof [[PROF1:![0-9]+]]
; CHECK-NEXT: ret i32 [[RESULT_SROA_SPECULATED]]
;
entry:
Expand All @@ -53,7 +53,7 @@ entry:
%v1 = load i32, ptr %a1

%cond = icmp sle i32 %v0, %v1
%select = select i1 %cond, ptr %a1, ptr %a
%select = select i1 %cond, ptr %a1, ptr %a, !prof !1

%result = load i32, ptr %select
ret i32 %result
Expand Down Expand Up @@ -870,3 +870,17 @@ define i8 @volatile_select(ptr %p, i1 %b) {
%v2 = load i8, ptr %px
ret i8 %v2
}

!0 = !{!"function_entry_count", i32 10}
!1 = !{!"branch_weights", i32 3, i32 5}
;.
; CHECK-PRESERVE-CFG: attributes #[[ATTR0:[0-9]+]] = { sanitize_address }
;.
; CHECK-MODIFY-CFG: attributes #[[ATTR0:[0-9]+]] = { sanitize_address }
;.
; CHECK-PRESERVE-CFG: [[META0:![0-9]+]] = !{!"function_entry_count", i32 10}
; CHECK-PRESERVE-CFG: [[PROF1]] = !{!"branch_weights", i32 3, i32 5}
;.
; CHECK-MODIFY-CFG: [[META0:![0-9]+]] = !{!"function_entry_count", i32 10}
; CHECK-MODIFY-CFG: [[PROF1]] = !{!"branch_weights", i32 3, i32 5}
;.
3 changes: 0 additions & 3 deletions llvm/utils/profcheck-xfail.txt
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Expand Up @@ -1312,14 +1312,11 @@ Transforms/SimpleLoopUnswitch/pr60736.ll
Transforms/SimpleLoopUnswitch/trivial-unswitch-freeze-individual-conditions.ll
Transforms/SimpleLoopUnswitch/trivial-unswitch.ll
Transforms/SimpleLoopUnswitch/trivial-unswitch-logical-and-or.ll
Transforms/SROA/addrspacecast.ll
Transforms/SROA/phi-and-select.ll
Transforms/SROA/phi-gep.ll
Transforms/SROA/scalable-vectors-with-known-vscale.ll
Transforms/SROA/select-gep.ll
Transforms/SROA/select-load.ll
Transforms/SROA/slice-width.ll
Transforms/SROA/std-clamp.ll
Transforms/SROA/vector-conversion.ll
Transforms/SROA/vector-promotion-cannot-tree-structure-merge.ll
Transforms/SROA/vector-promotion.ll
Expand Down
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