Skip to content

[RISCV] Don't transfer (select c, t, f) to Zicond when optimizing for size #163501

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 3 commits into
base: main
Choose a base branch
from
Open

[RISCV] Don't transfer (select c, t, f) to Zicond when optimizing for size #163501

Show file tree
Hide file tree
Changes from 1 commit
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
8721e00
[RISCV] Pre-commit
tclin914 Oct 15, 2025
f916782
[RISCV] Don't transfer (select c, t, f) to Zicond when optimizing for…
tclin914 Oct 15, 2025
57622d9
address comment
tclin914 Oct 16, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
7 changes: 5 additions & 2 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -9458,8 +9458,11 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
}

// (select c, t, f) -> (or (czero_eqz t, c), (czero_nez f, c))
// Unless we have the short forward branch optimization.
if (!Subtarget.hasConditionalMoveFusion())
// Unless we have the short forward branch optimization or CondV has one use
// when optimizaing for size.
if (!Subtarget.hasConditionalMoveFusion() &&
(!DAG.shouldOptForSize() ||
(DAG.shouldOptForSize() && CondV.hasOneUse())))
return DAG.getNode(
ISD::OR, DL, VT,
DAG.getNode(RISCVISD::CZERO_EQZ, DL, VT, TrueV, CondV),
Expand Down
26 changes: 14 additions & 12 deletions llvm/test/CodeGen/RISCV/condops.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1364,12 +1364,13 @@ define i64 @basic_optsize(i1 zeroext %rc, i64 %rs1, i64 %rs2) optsize {
;
; RV32XVENTANACONDOPS-LABEL: basic_optsize:
; RV32XVENTANACONDOPS: # %bb.0:
; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a0
; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a0
; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a4, a0
; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0
; RV32XVENTANACONDOPS-NEXT: or a0, a1, a3
; RV32XVENTANACONDOPS-NEXT: or a1, a2, a4
; RV32XVENTANACONDOPS-NEXT: bnez a0, .LBB23_2
; RV32XVENTANACONDOPS-NEXT: # %bb.1:
; RV32XVENTANACONDOPS-NEXT: mv a1, a3
; RV32XVENTANACONDOPS-NEXT: mv a2, a4
; RV32XVENTANACONDOPS-NEXT: .LBB23_2:
; RV32XVENTANACONDOPS-NEXT: mv a0, a1
; RV32XVENTANACONDOPS-NEXT: mv a1, a2
; RV32XVENTANACONDOPS-NEXT: ret
;
; RV64XVENTANACONDOPS-LABEL: basic_optsize:
Expand All @@ -1387,12 +1388,13 @@ define i64 @basic_optsize(i1 zeroext %rc, i64 %rs1, i64 %rs2) optsize {
;
; RV32ZICOND-LABEL: basic_optsize:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: czero.nez a3, a3, a0
; RV32ZICOND-NEXT: czero.eqz a1, a1, a0
; RV32ZICOND-NEXT: czero.nez a4, a4, a0
; RV32ZICOND-NEXT: czero.eqz a2, a2, a0
; RV32ZICOND-NEXT: or a0, a1, a3
; RV32ZICOND-NEXT: or a1, a2, a4
; RV32ZICOND-NEXT: bnez a0, .LBB23_2
; RV32ZICOND-NEXT: # %bb.1:
; RV32ZICOND-NEXT: mv a1, a3
; RV32ZICOND-NEXT: mv a2, a4
; RV32ZICOND-NEXT: .LBB23_2:
; RV32ZICOND-NEXT: mv a0, a1
; RV32ZICOND-NEXT: mv a1, a2
; RV32ZICOND-NEXT: ret
;
; RV64ZICOND-LABEL: basic_optsize:
Expand Down