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[X86]: Rewrite demorgan rule for ANDN #163789

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[X86]: Rewrite demorgan rule for ANDN #163789

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ee35653
[X86]: Reassoc demorgan rule for ANDN
kper Oct 16, 2025
deda338
[X86]: Removed obsolete code
kper Oct 16, 2025
cdb57ef
[DAG]: Reassoc demorgan rule for ANDN
kper Oct 16, 2025
9e4103d
[DAG]: Fixed type
kper Oct 16, 2025
cf6ee58
[X86]: Updated tests
kper Oct 16, 2025
cef0067
[DAG]: Updated tests
kper Oct 16, 2025
e31e5ab
[DAG]: Updated tests
kper Oct 17, 2025
cf9da83
Revert "[DAG]: Updated tests"
kper Oct 18, 2025
3a90a69
Revert "[DAG]: Updated tests"
kper Oct 18, 2025
1245b6b
[DAG]: Rewrite `~(a | b | c)` into `~a & ~b & ~c`
kper Oct 18, 2025
746b101
[X86]: Created new test
kper Oct 18, 2025
f237020
[DAG]: Run fmt
kper Oct 18, 2025
956b849
[AArch64]: Updated tests
kper Oct 18, 2025
643e4d5
[X86]: Updated tests
kper Oct 18, 2025
e2032ef
[PowerPC]: Updated tests
kper Oct 18, 2025
5218588
[X86]: Removed reversing of rewriting demorgan
kper Oct 18, 2025
de10f4a
[X86][PowerPC][AArch64]: Updated tests
kper Oct 18, 2025
c95c10a
[LoongArch][SystemZ]: Updated tests
kper Oct 22, 2025
3681932
[AArch64][PowerPC]: Reverting some updates
kper Oct 22, 2025
b3ec648
[X86]: Removed comment
kper Oct 22, 2025
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25 changes: 25 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Expand Up @@ -10197,6 +10197,31 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
}
}

// fold (not (or A, or(B, C))) -> and(not(A), and(not(B), not(C))
if (TLI.hasAndNot(SDValue(N, 0))) {
// If we have AndNot then it is profitable to apply demorgan to make use
// of the machine instruction.
Comment on lines +10202 to +10203
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I would argue that this fold is not profitable at all on its own. It is only profitable when combined into a larger pattern like ~(A|B|C).

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Yeah that's also my impression :/
I have been updating the rest of the .ll after I "fixed" the infinite loop. And, it doesn't look so good.
I will try the larger pattern and let's see what the result is.

SDValue A;
SDValue B;
SDValue C;
APInt Cst;
if (sd_match(N, m_Xor(m_Or(m_Value(A), m_Or(m_Value(B), m_Value(C))),
m_ConstInt(Cst))) &&
Cst.isAllOnes()) {
auto Ty = N->getValueType(0);

auto NegA =
DAG.getNode(ISD::XOR, DL, VT, A, DAG.getConstant(Cst, DL, Ty));
auto NegB =
DAG.getNode(ISD::XOR, DL, VT, B, DAG.getConstant(Cst, DL, Ty));
auto NegC =
DAG.getNode(ISD::XOR, DL, VT, C, DAG.getConstant(Cst, DL, Ty));

return DAG.getNode(ISD::AND, DL, VT, NegA,
DAG.getNode(ISD::AND, DL, VT, NegB, NegC));
}
}

return SDValue();
}

Expand Down
5 changes: 0 additions & 5 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Expand Up @@ -55615,11 +55615,6 @@ static SDValue combineAndnp(SDNode *N, SelectionDAG &DAG,

// Folds for better commutativity:
if (N1->hasOneUse()) {
// ANDNP(x,NOT(y)) -> AND(NOT(x),NOT(y)) -> NOT(OR(X,Y)).
if (SDValue Not = IsNOT(N1, DAG))
return DAG.getNOT(
DL, DAG.getNode(ISD::OR, DL, VT, N0, DAG.getBitcast(VT, Not)), VT);

// ANDNP(x,PSHUFB(y,z)) -> PSHUFB(y,OR(z,x))
// Zero out elements by setting the PSHUFB mask value to 0xFF.
if (DAG.ComputeNumSignBits(N0) == EltSizeInBits) {
Expand Down
139 changes: 82 additions & 57 deletions llvm/test/CodeGen/AArch64/ctlz.ll
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Expand Up @@ -276,18 +276,23 @@ define <2 x i64> @v2i64(<2 x i64> %d) {
; CHECK-SD-LABEL: v2i64:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: ushr v1.2d, v0.2d, #1
; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: ushr v1.2d, v0.2d, #2
; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: ushr v1.2d, v0.2d, #4
; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: ushr v1.2d, v0.2d, #8
; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: ushr v1.2d, v0.2d, #16
; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: ushr v1.2d, v0.2d, #32
; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: orr v2.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: mvn v0.16b, v0.16b
; CHECK-SD-NEXT: ushr v3.2d, v2.2d, #2
; CHECK-SD-NEXT: bic v0.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: orr v2.16b, v2.16b, v3.16b
; CHECK-SD-NEXT: bic v0.16b, v0.16b, v3.16b
; CHECK-SD-NEXT: ushr v4.2d, v2.2d, #4
; CHECK-SD-NEXT: orr v2.16b, v2.16b, v4.16b
; CHECK-SD-NEXT: bic v0.16b, v0.16b, v4.16b
; CHECK-SD-NEXT: ushr v1.2d, v2.2d, #8
; CHECK-SD-NEXT: orr v2.16b, v2.16b, v1.16b
; CHECK-SD-NEXT: bic v0.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: ushr v3.2d, v2.2d, #16
; CHECK-SD-NEXT: orr v1.16b, v2.16b, v3.16b
; CHECK-SD-NEXT: bic v0.16b, v0.16b, v3.16b
; CHECK-SD-NEXT: ushr v1.2d, v1.2d, #32
; CHECK-SD-NEXT: bic v0.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: cnt v0.16b, v0.16b
; CHECK-SD-NEXT: uaddlp v0.8h, v0.16b
; CHECK-SD-NEXT: uaddlp v0.4s, v0.8h
Expand All @@ -314,34 +319,44 @@ define <3 x i64> @v3i64(<3 x i64> %d) {
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-SD-NEXT: ushr v4.2d, v2.2d, #1
; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
; CHECK-SD-NEXT: orr v6.16b, v2.16b, v4.16b
; CHECK-SD-NEXT: mvn v2.16b, v2.16b
; CHECK-SD-NEXT: ushr v1.2d, v0.2d, #1
; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: ushr v1.2d, v2.2d, #1
; CHECK-SD-NEXT: ushr v3.2d, v0.2d, #2
; CHECK-SD-NEXT: orr v1.16b, v2.16b, v1.16b
; CHECK-SD-NEXT: orr v0.16b, v0.16b, v3.16b
; CHECK-SD-NEXT: ushr v2.2d, v1.2d, #2
; CHECK-SD-NEXT: ushr v3.2d, v0.2d, #4
; CHECK-SD-NEXT: orr v1.16b, v1.16b, v2.16b
; CHECK-SD-NEXT: orr v0.16b, v0.16b, v3.16b
; CHECK-SD-NEXT: ushr v2.2d, v1.2d, #4
; CHECK-SD-NEXT: ushr v3.2d, v0.2d, #8
; CHECK-SD-NEXT: orr v1.16b, v1.16b, v2.16b
; CHECK-SD-NEXT: orr v0.16b, v0.16b, v3.16b
; CHECK-SD-NEXT: ushr v2.2d, v1.2d, #8
; CHECK-SD-NEXT: ushr v3.2d, v0.2d, #16
; CHECK-SD-NEXT: orr v1.16b, v1.16b, v2.16b
; CHECK-SD-NEXT: orr v0.16b, v0.16b, v3.16b
; CHECK-SD-NEXT: ushr v2.2d, v1.2d, #16
; CHECK-SD-NEXT: ushr v3.2d, v0.2d, #32
; CHECK-SD-NEXT: orr v1.16b, v1.16b, v2.16b
; CHECK-SD-NEXT: orr v0.16b, v0.16b, v3.16b
; CHECK-SD-NEXT: ushr v2.2d, v1.2d, #32
; CHECK-SD-NEXT: ushr v7.2d, v6.2d, #2
; CHECK-SD-NEXT: bic v2.16b, v2.16b, v4.16b
; CHECK-SD-NEXT: orr v3.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: mvn v0.16b, v0.16b
; CHECK-SD-NEXT: orr v1.16b, v1.16b, v2.16b
; CHECK-SD-NEXT: orr v6.16b, v6.16b, v7.16b
; CHECK-SD-NEXT: bic v2.16b, v2.16b, v7.16b
; CHECK-SD-NEXT: ushr v5.2d, v3.2d, #2
; CHECK-SD-NEXT: bic v0.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: ushr v17.2d, v6.2d, #4
; CHECK-SD-NEXT: orr v3.16b, v3.16b, v5.16b
; CHECK-SD-NEXT: bic v0.16b, v0.16b, v5.16b
; CHECK-SD-NEXT: orr v6.16b, v6.16b, v17.16b
; CHECK-SD-NEXT: bic v2.16b, v2.16b, v17.16b
; CHECK-SD-NEXT: ushr v16.2d, v3.2d, #4
; CHECK-SD-NEXT: ushr v4.2d, v6.2d, #8
; CHECK-SD-NEXT: orr v3.16b, v3.16b, v16.16b
; CHECK-SD-NEXT: bic v0.16b, v0.16b, v16.16b
; CHECK-SD-NEXT: orr v6.16b, v6.16b, v4.16b
; CHECK-SD-NEXT: bic v2.16b, v2.16b, v4.16b
; CHECK-SD-NEXT: ushr v1.2d, v3.2d, #8
; CHECK-SD-NEXT: orr v3.16b, v3.16b, v1.16b
; CHECK-SD-NEXT: bic v0.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: ushr v5.2d, v3.2d, #16
; CHECK-SD-NEXT: orr v1.16b, v3.16b, v5.16b
; CHECK-SD-NEXT: ushr v3.2d, v6.2d, #16
; CHECK-SD-NEXT: bic v0.16b, v0.16b, v5.16b
; CHECK-SD-NEXT: ushr v1.2d, v1.2d, #32
; CHECK-SD-NEXT: orr v4.16b, v6.16b, v3.16b
; CHECK-SD-NEXT: bic v0.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: bic v1.16b, v2.16b, v3.16b
; CHECK-SD-NEXT: ushr v2.2d, v4.2d, #32
; CHECK-SD-NEXT: cnt v0.16b, v0.16b
; CHECK-SD-NEXT: mvn v1.16b, v1.16b
; CHECK-SD-NEXT: bic v1.16b, v1.16b, v2.16b
; CHECK-SD-NEXT: cnt v1.16b, v1.16b
; CHECK-SD-NEXT: uaddlp v0.8h, v0.16b
; CHECK-SD-NEXT: uaddlp v0.4s, v0.8h
Expand Down Expand Up @@ -377,30 +392,40 @@ define <4 x i64> @v4i64(<4 x i64> %d) {
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: ushr v2.2d, v0.2d, #1
; CHECK-SD-NEXT: ushr v3.2d, v1.2d, #1
; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b
; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b
; CHECK-SD-NEXT: ushr v2.2d, v0.2d, #2
; CHECK-SD-NEXT: ushr v3.2d, v1.2d, #2
; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b
; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b
; CHECK-SD-NEXT: ushr v2.2d, v0.2d, #4
; CHECK-SD-NEXT: ushr v3.2d, v1.2d, #4
; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b
; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b
; CHECK-SD-NEXT: ushr v2.2d, v0.2d, #8
; CHECK-SD-NEXT: ushr v3.2d, v1.2d, #8
; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b
; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b
; CHECK-SD-NEXT: ushr v2.2d, v0.2d, #16
; CHECK-SD-NEXT: ushr v3.2d, v1.2d, #16
; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b
; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b
; CHECK-SD-NEXT: ushr v2.2d, v0.2d, #32
; CHECK-SD-NEXT: ushr v3.2d, v1.2d, #32
; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b
; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b
; CHECK-SD-NEXT: orr v4.16b, v0.16b, v2.16b
; CHECK-SD-NEXT: orr v5.16b, v1.16b, v3.16b
; CHECK-SD-NEXT: mvn v0.16b, v0.16b
; CHECK-SD-NEXT: mvn v1.16b, v1.16b
; CHECK-SD-NEXT: ushr v6.2d, v4.2d, #2
; CHECK-SD-NEXT: ushr v7.2d, v5.2d, #2
; CHECK-SD-NEXT: bic v0.16b, v0.16b, v2.16b
; CHECK-SD-NEXT: bic v1.16b, v1.16b, v3.16b
; CHECK-SD-NEXT: orr v4.16b, v4.16b, v6.16b
; CHECK-SD-NEXT: orr v5.16b, v5.16b, v7.16b
; CHECK-SD-NEXT: bic v0.16b, v0.16b, v6.16b
; CHECK-SD-NEXT: bic v1.16b, v1.16b, v7.16b
; CHECK-SD-NEXT: ushr v16.2d, v4.2d, #4
; CHECK-SD-NEXT: ushr v17.2d, v5.2d, #4
; CHECK-SD-NEXT: orr v4.16b, v4.16b, v16.16b
; CHECK-SD-NEXT: orr v5.16b, v5.16b, v17.16b
; CHECK-SD-NEXT: bic v0.16b, v0.16b, v16.16b
; CHECK-SD-NEXT: bic v1.16b, v1.16b, v17.16b
; CHECK-SD-NEXT: ushr v2.2d, v4.2d, #8
; CHECK-SD-NEXT: ushr v3.2d, v5.2d, #8
; CHECK-SD-NEXT: orr v4.16b, v4.16b, v2.16b
; CHECK-SD-NEXT: orr v5.16b, v5.16b, v3.16b
; CHECK-SD-NEXT: bic v0.16b, v0.16b, v2.16b
; CHECK-SD-NEXT: bic v1.16b, v1.16b, v3.16b
; CHECK-SD-NEXT: ushr v6.2d, v4.2d, #16
; CHECK-SD-NEXT: ushr v7.2d, v5.2d, #16
; CHECK-SD-NEXT: orr v2.16b, v4.16b, v6.16b
; CHECK-SD-NEXT: orr v3.16b, v5.16b, v7.16b
; CHECK-SD-NEXT: bic v0.16b, v0.16b, v6.16b
; CHECK-SD-NEXT: bic v1.16b, v1.16b, v7.16b
; CHECK-SD-NEXT: ushr v2.2d, v2.2d, #32
; CHECK-SD-NEXT: ushr v3.2d, v3.2d, #32
; CHECK-SD-NEXT: bic v0.16b, v0.16b, v2.16b
; CHECK-SD-NEXT: bic v1.16b, v1.16b, v3.16b
; CHECK-SD-NEXT: cnt v0.16b, v0.16b
; CHECK-SD-NEXT: cnt v1.16b, v1.16b
; CHECK-SD-NEXT: uaddlp v0.8h, v0.16b
Expand Down
27 changes: 16 additions & 11 deletions llvm/test/CodeGen/AArch64/eon.ll
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@@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
; RUN: llc %s -pass-remarks-missed=gisel* -mtriple=aarch64-none-linux-gnu -global-isel -o - 2>&1 | FileCheck %s

Expand All @@ -6,8 +7,9 @@
; Check that the eon instruction is generated instead of eor,movn
define i64 @test1(i64 %a, i64 %b, i64 %c) {
; CHECK-LABEL: test1:
; CHECK: eon
; CHECK: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: eon x0, x0, x1, lsl #4
; CHECK-NEXT: ret
entry:
%shl = shl i64 %b, 4
%neg = xor i64 %a, -1
Expand All @@ -18,10 +20,11 @@ entry:
; Same check with multiple uses of %neg
define i64 @test2(i64 %a, i64 %b, i64 %c) {
; CHECK-LABEL: test2:
; CHECK: eon
; CHECK: eon
; CHECK: lsl
; CHECK: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: eon x8, x0, x1, lsl #4
; CHECK-NEXT: eon x9, x2, x1, lsl #4
; CHECK-NEXT: lsl x0, x8, x9
; CHECK-NEXT: ret
entry:
%shl = shl i64 %b, 4
%neg = xor i64 %shl, -1
Expand All @@ -34,8 +37,9 @@ entry:
; Check that eon is generated if the xor is a disjoint or.
define i64 @disjoint_or(i64 %a, i64 %b) {
; CHECK-LABEL: disjoint_or:
; CHECK: eon
; CHECK: ret
; CHECK: // %bb.0:
; CHECK-NEXT: eon x0, x0, x1
; CHECK-NEXT: ret
%or = or disjoint i64 %a, %b
%eon = xor i64 %or, -1
ret i64 %eon
Expand All @@ -44,9 +48,10 @@ define i64 @disjoint_or(i64 %a, i64 %b) {
; Check that eon is *not* generated if the or is not disjoint.
define i64 @normal_or(i64 %a, i64 %b) {
; CHECK-LABEL: normal_or:
; CHECK: orr
; CHECK: mvn
; CHECK: ret
; CHECK: // %bb.0:
; CHECK-NEXT: orr x8, x0, x1
; CHECK-NEXT: mvn x0, x8
; CHECK-NEXT: ret
%or = or i64 %a, %b
%not = xor i64 %or, -1
ret i64 %not
Expand Down
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