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[AMDGPU] 32-bit ABS is a legal DAG node #163907

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Merged
merged 2 commits into from
Oct 17, 2025
Merged

[AMDGPU] 32-bit ABS is a legal DAG node #163907

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1893053
Make 32-bit ABS is legal DAG node
LU-JOHN Oct 17, 2025
5a10d95
Do smax transform in separate PR
LU-JOHN Oct 17, 2025
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4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -514,8 +514,8 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
MVT::i64, Custom);
setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);

setOperationAction({ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX}, MVT::i32,
Legal);
setOperationAction({ISD::ABS, ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX},
MVT::i32, Legal);

setOperationAction(
{ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF},
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7 changes: 7 additions & 0 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Expand Up @@ -14945,6 +14945,13 @@ SDValue SITargetLowering::performMinMaxCombine(SDNode *N,
}
}

// max(x, neg(x)) -> abs(x)
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Can we do this in the generic part?

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Can we do this in the generic part?

All ISD::SMAX nodes are sent to this function from the switch in PerformDAGCombine. I don't see where else to put it. This function is intended to process min or max nodes so it makes sense to put it here.

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I don't see any AMDGPU specific ISD here so why can't this be done in the generic combine part?

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Removed smax transformation from this PR. Will do it in a separate generic PR.

if (Opc == ISD::SMAX && VT == MVT::i32) {
SDValue Value;
if (sd_match(N, m_SMax(m_Value(Value), m_Neg(m_Deferred(Value)))))
return DAG.getNode(ISD::ABS, SDLoc(N), VT, Value);
}

// min(max(x, K0), K1), K0 < K1 -> med3(x, K0, K1)
// max(min(x, K0), K1), K1 < K0 -> med3(x, K1, K0)
if (Opc == ISD::SMIN && Op0.getOpcode() == ISD::SMAX && Op0.hasOneUse()) {
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