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[mlir][rocdl] Adds cvt.scalef32.pk16.* and cvt.scalef32.sr.pk16.* operations #164014

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Merged
merged 2 commits into from
Oct 18, 2025
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[mlir][rocdl] Adds cvt.scalef32.pk16.* and cvt.scalef32.sr.pk16.* operations #164014

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4f6ba43
Add upscaling for cvt.scalef32.pk16
amd-eochoalo Oct 15, 2025
2889c04
Add scalef32.pk16 operations
amd-eochoalo Oct 15, 2025
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37 changes: 37 additions & 0 deletions mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1143,6 +1143,7 @@ foreach smallT = [
ScaleArgInfo<ROCDL_V16BF16Type, "Bf16">,
ScaleArgInfo<ROCDL_V16F32Type, "F32">,
] in {
// Up-scaling
def ROCDL_CvtPkScalePk16 # largeT.nameForOp # smallT.nameForOp # Op :
ROCDL_ConcreteNonMemIntrOp<"cvt.scale.pk16." # largeT.name # "." # smallT.name,
[Pure], 1, [2], ["scaleSel"]>,
Expand All @@ -1158,6 +1159,42 @@ foreach smallT = [
}];

}

// Down-scaling
def ROCDL_CvtScaleF32Pk16 # smallT.nameForOp # largeT.nameForOp # Op :
ROCDL_ConcreteNonMemIntrOp<"cvt.scalef32.pk16." # smallT.name # "." # largeT.name,
[Pure], 1>,
Arguments<(ins largeT.type:$src, F32:$scale)> {
let results = (outs smallT.type:$res);
let summary = "Scale and convert packed "
# largeT.name # " to packed " # smallT.name ;
let description = [{
Convert 8 packed }] # largeT.name # [{ values to packed }]
# smallT.name # [{, multiplying by the exponent part of `scale`
before doing so. This op is for gfx1250+ arch.
}];
let assemblyFormat = [{
attr-dict $src `,` $scale `:` type($res)
}];
}

def ROCDL_CvtScaleF32SrPk16 # smallT.nameForOp # largeT.nameForOp # Op :
ROCDL_ConcreteNonMemIntrOp<"cvt.scalef32.sr.pk16." # smallT.name # "." # largeT.name,
[Pure], 1>,
Arguments<(ins largeT.type:$src, I32:$seed, F32:$scale)> {
let results = (outs smallT.type:$res);
let summary = "Scale and convert packed "
# largeT.name # " to packed " # smallT.name # " with stochastic rounding";
let description = [{
Convert 8 packed }] # largeT.name # [{ values to packed }]
# smallT.name # [{, multiplying by the exponent part of `scale`
before doing so and apply stochastic rounding. This op is for gfx1250+ arch.
}];
let assemblyFormat = [{
attr-dict $src `,` $seed `,` $scale `:` type($res)
}];
}

} // foreach largeT
} // foreach smallTOp

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51 changes: 51 additions & 0 deletions mlir/test/Dialect/LLVMIR/rocdl.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -1211,6 +1211,57 @@ llvm.func @rocdl.cvt.scale.pk16(%v3xi32: vector<3xi32>, %scale:i32) {

// -----

// CHECK-LABEL: rocdl.cvt.scalef32.pk16
llvm.func @rocdl.cvt.scalef32.pk16(%v16xf32: vector<16xf32>,
%v16xf16: vector<16xf16>,
%v16xbf16: vector<16xbf16>,
%scale: f32) {

// CHECK: rocdl.cvt.scalef32.pk16.fp6.f16
%0 = rocdl.cvt.scalef32.pk16.fp6.f16 %v16xf16, %scale : vector<3xi32>
// CHECK: rocdl.cvt.scalef32.pk16.fp6.bf16
%1 = rocdl.cvt.scalef32.pk16.fp6.bf16 %v16xbf16, %scale : vector<3xi32>
// CHECK: rocdl.cvt.scalef32.pk16.fp6.f32
%2 = rocdl.cvt.scalef32.pk16.fp6.f32 %v16xf32, %scale : vector<3xi32>

// CHECK: rocdl.cvt.scalef32.pk16.bf6.f16
%3 = rocdl.cvt.scalef32.pk16.bf6.f16 %v16xf16, %scale : vector<3xi32>
// CHECK: rocdl.cvt.scalef32.pk16.bf6.bf16
%4 = rocdl.cvt.scalef32.pk16.bf6.bf16 %v16xbf16, %scale : vector<3xi32>
// CHECK: rocdl.cvt.scalef32.pk16.bf6.f32
%5 = rocdl.cvt.scalef32.pk16.bf6.f32 %v16xf32, %scale : vector<3xi32>

llvm.return
}

// -----

// CHECK-LABEL: rocdl.cvt.scalef32.sr.pk16
llvm.func @rocdl.cvt.scalef32.sr.pk16(%v16xf32: vector<16xf32>,
%v16xf16: vector<16xf16>,
%v16xbf16: vector<16xbf16>,
%seed: i32,
%scale: f32) {

// CHECK: rocdl.cvt.scalef32.sr.pk16.fp6.f16
%0 = rocdl.cvt.scalef32.sr.pk16.fp6.f16 %v16xf16, %seed, %scale : vector<3xi32>
// CHECK: rocdl.cvt.scalef32.sr.pk16.fp6.bf16
%1 = rocdl.cvt.scalef32.sr.pk16.fp6.bf16 %v16xbf16, %seed, %scale : vector<3xi32>
// CHECK: rocdl.cvt.scalef32.sr.pk16.fp6.f32
%2 = rocdl.cvt.scalef32.sr.pk16.fp6.f32 %v16xf32, %seed, %scale : vector<3xi32>

// CHECK: rocdl.cvt.scalef32.sr.pk16.bf6.f16
%3 = rocdl.cvt.scalef32.sr.pk16.bf6.f16 %v16xf16, %seed, %scale : vector<3xi32>
// CHECK: rocdl.cvt.scalef32.sr.pk16.bf6.bf16
%4 = rocdl.cvt.scalef32.sr.pk16.bf6.bf16 %v16xbf16, %seed, %scale : vector<3xi32>
// CHECK: rocdl.cvt.scalef32.sr.pk16.bf6.f32
%5 = rocdl.cvt.scalef32.sr.pk16.bf6.f32 %v16xf32, %seed, %scale : vector<3xi32>

llvm.return
}

// -----

// expected-error@below {{attribute attached to unexpected op}}
func.func private @expected_llvm_func() attributes { rocdl.kernel }

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46 changes: 46 additions & 0 deletions mlir/test/Target/LLVMIR/rocdl.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -1477,6 +1477,52 @@ llvm.func @rocdl.cvt.scale.pk16(%v3xi32: vector<3xi32>, %scale:i32) {
llvm.return
}

// CHECK-LABEL: rocdl.cvt.scalef32.pk16
// CHECK-SAME:(<16 x float> %[[V16F32:.+]], <16 x half> %[[V16F16:.+]], <16 x bfloat> %[[V16BF16:.+]], float %[[SCALE:.+]])
llvm.func @rocdl.cvt.scalef32.pk16(%v16xf32: vector<16xf32>, %v16xf16: vector<16xf16>, %v16xbf16: vector<16xbf16>, %scale: f32) {

// CHECK: call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f16(<16 x half> %[[V16F16]], float %[[SCALE]])
%0 = rocdl.cvt.scalef32.pk16.fp6.f16 %v16xf16, %scale : vector<3xi32>
// CHECK: call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.bf16(<16 x bfloat> %[[V16BF16]], float %[[SCALE]])
%1 = rocdl.cvt.scalef32.pk16.fp6.bf16 %v16xbf16, %scale : vector<3xi32>
// CHECK: call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f32(<16 x float> %[[V16F32]], float %[[SCALE]])
%2 = rocdl.cvt.scalef32.pk16.fp6.f32 %v16xf32, %scale : vector<3xi32>

// CHECK: call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.f16(<16 x half> %[[V16F16]], float %[[SCALE]])
%3 = rocdl.cvt.scalef32.pk16.bf6.f16 %v16xf16, %scale : vector<3xi32>
// CHECK: call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.bf16(<16 x bfloat> %[[V16BF16]], float %[[SCALE]])
%4 = rocdl.cvt.scalef32.pk16.bf6.bf16 %v16xbf16, %scale : vector<3xi32>
// CHECK: call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.f32(<16 x float> %[[V16F32]], float %[[SCALE]])
%5 = rocdl.cvt.scalef32.pk16.bf6.f32 %v16xf32, %scale : vector<3xi32>

llvm.return
}

// CHECK-LABEL: rocdl.cvt.scalef32.sr.pk16
// CHECK-SAME:(<16 x float> %[[V16F32:.+]], <16 x half> %[[V16F16:.+]], <16 x bfloat> %[[V16BF16:.+]], i32 %[[SEED:.+]], float %[[SCALE:.+]])
llvm.func @rocdl.cvt.scalef32.sr.pk16(%v16xf32: vector<16xf32>,
%v16xf16: vector<16xf16>,
%v16xbf16: vector<16xbf16>,
%seed: i32,
%scale: f32) {

// CHECK: call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.f16(<16 x half> %[[V16F16]], i32 %[[SEED]], float %[[SCALE]])
%0 = rocdl.cvt.scalef32.sr.pk16.fp6.f16 %v16xf16, %seed, %scale : vector<3xi32>
// CHECK: call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.bf16(<16 x bfloat> %[[V16BF16]], i32 %[[SEED]], float %[[SCALE]])
%1 = rocdl.cvt.scalef32.sr.pk16.fp6.bf16 %v16xbf16, %seed, %scale : vector<3xi32>
// CHECK: call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.f32(<16 x float> %[[V16F32]], i32 %[[SEED]], float %[[SCALE]])
%2 = rocdl.cvt.scalef32.sr.pk16.fp6.f32 %v16xf32, %seed, %scale : vector<3xi32>

// CHECK: call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.f16(<16 x half> %[[V16F16]], i32 %[[SEED]], float %[[SCALE]])
%3 = rocdl.cvt.scalef32.sr.pk16.bf6.f16 %v16xf16, %seed, %scale : vector<3xi32>
// CHECK: call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.bf16(<16 x bfloat> %[[V16BF16]], i32 %[[SEED]], float %[[SCALE]])
%4 = rocdl.cvt.scalef32.sr.pk16.bf6.bf16 %v16xbf16, %seed, %scale : vector<3xi32>
// CHECK: call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.f32(<16 x float> %[[V16F32]], i32 %[[SEED]], float %[[SCALE]])
%5 = rocdl.cvt.scalef32.sr.pk16.bf6.f32 %v16xf32, %seed, %scale : vector<3xi32>

llvm.return
}

// CHECK-DAG: attributes #[[$KERNEL_ATTRS]] = { "amdgpu-flat-work-group-size"="1,256" "uniform-work-group-size"="true" }
// CHECK-DAG: attributes #[[$KERNEL_WORKGROUP_ATTRS]] = { "amdgpu-flat-work-group-size"="1,1024"
// CHECK-DAG: attributes #[[$KNOWN_BLOCK_SIZE_ATTRS]] = { "amdgpu-flat-work-group-size"="128,128"
Expand Down