[CT] Updated CT X86 test for the LLVM 21 changes#164045

Closed

wizardengineer wants to merge 63 commits intollvm:mainfrom

trail-of-forks:julius/x86-update-test

Commits on Oct 17, 2025

[CT]implementation of ct.select intrinsics and clang frontend changes for X86 architecture (#21)

kumarak
authored and
wizardengineer
committed
[CT] Expand vector CTSELECT (#26)

frabert
authored and
wizardengineer
committed
[CT] Fix promotion of (CT)SELECT nodes (#24)

frabert
authored and
wizardengineer
committed
[CT] Expand float and integer CTSELECTs (#27)

frabert
authored and
wizardengineer
committed
Enchance CT Checks for all supported Archs
wizardengineer
committed
Initial implement for fallback method
wizardengineer
committed
Added test for RISCVs, MIPs and WebAsm
wizardengineer
committed
Used a more generic and simpler approach for managing NoMerge flag
wizardengineer
committed
[CT] Implement CTSELECT pseudo instruction for AArch64

frabert
authored and
wizardengineer
committed
Move pseudo instruction expansion to post RA target specific expansion pass and bundle the instructions (#31)

kumarak
authored and
wizardengineer
committed
Added guards for non-integral pointers
wizardengineer
committed
Added support for Float/Double data types
wizardengineer
committed
Added support for Vector types
wizardengineer
committed
[CT] Used sext for normalizing the predicate
wizardengineer
committed
Added specific test; cmovznz4
wizardengineer
committed
[CT] These changes reflect the current fallback changes. Which is was merge to our ct-llvmorg-20.1.4 branch
wizardengineer
committed
[CT] Lower CTSELECT in post-RA pass for AArch64

frabert
authored and
wizardengineer
committed
[CT] Added support for Scalable Vector types
wizardengineer
committed
Changes to for DAG Chaining
wizardengineer
committed
[CT] Added diffs for webasm tests
wizardengineer
committed
[CT] Removed NoMerge flag and added chain dependency between both ANDs
wizardengineer
committed
[CT] Added both createProtect function for chaining and for NoMerge Flag
wizardengineer
committed
[CT] Fix for x86 floating point vector types
wizardengineer
committed
[CT] check for xmm0 register as live and handle accordingly

kumarak
authored and
wizardengineer
committed
[CT] save and restore XMM0 for using as mask register

kumarak
authored and
wizardengineer
committed
[CT] Move floating point logic to right place
wizardengineer
committed
[CT] update handling of mask and remove avx512 pseudo and usage pattern

kumarak
authored and
wizardengineer
committed
[CT] report error on vector types with avx512 and improve lower ctselect

kumarak
authored and
wizardengineer
committed
[CT] add back support for v8f16 vector types that was removed

kumarak
authored and
wizardengineer
committed
[CT] disable bundling for vector types

kumarak
authored and
wizardengineer
committed
[CT] legalize vector types and remove error reporting for 512 bits vectors

kumarak
authored and
wizardengineer
committed
[CT]implementation of ct.select intrinsics and clang frontend changes for X86 architecture

kumarak
authored and
wizardengineer
committed
[CT] WIP: Implement CTSELECT for ARM

frabert
authored and
wizardengineer
committed
WIP: integrate the ctselect intrinsic so it can be recognised and lowered, connecting it to the lowering function

kaoudis
authored and
wizardengineer
committed
[CT] Expand float and integer CTSELECTs (#27)

frabert
authored and
wizardengineer
committed
[CT] initial ARM lowering to pseudo and expansion to bitwise

kaoudis
authored and
wizardengineer
committed
[CT] code quality improvements to ARM implementation (#43)

kaoudis
authored and
wizardengineer
committed
[CT][NFC] Added Mips code-gen tests that's affected by DAG Chaining
wizardengineer
committed
[CT] implements thumb1 and thumb2 lowering for ARM back end

kaoudis
authored and
wizardengineer
committed
[CT] removes constant folding from our intrinisic

kaoudis
authored and
wizardengineer
committed
[CT] do not allow duplication and do not touch memory

kaoudis
authored and
wizardengineer
committed
[CT] fix codegen for thumb1 instructions

kumarak
authored and
wizardengineer
committed
[CT] Fix legalization of vectors with small lanes on AArch64

frabert
authored and
wizardengineer
committed
[CT] create instruction bundle during post RA expansion

kumarak
authored and
wizardengineer
committed
[CT] record last intstruction during bundling for x86

kumarak
authored and
wizardengineer
committed
[CT] Integer constant-time selection without CMOV on i386

hbrodin
authored and
wizardengineer
committed
[CT] Make cmov predicates more stringent

hbrodin
authored and
wizardengineer
committed
[CT] Implement constant-time CTSELECT for i386 targets without CMOV

hbrodin
authored and
wizardengineer
committed
[CT] VR64 support

hbrodin
authored and
wizardengineer
committed
[CT] Fix bundle unpacking

hbrodin
authored and
wizardengineer
committed
[CT] Properly expand BUNDLEs on x86

hbrodin
authored and
wizardengineer
committed
[CT] Fix bundled sequence for ints

hbrodin
authored and
wizardengineer
committed
[CT] FP32 via integer ct-select

hbrodin
authored and
wizardengineer
committed
[CT] FP64 via two 32-bit integer ctselect

hbrodin
authored and
wizardengineer
committed
[CT] FP80 support via 32-bit integer ctselect

hbrodin
authored and
wizardengineer
committed
[CT] Optimize for when operands on stack already - skip FP

hbrodin
authored and
wizardengineer
committed
[CT] Update handling of floating type and emit pseudo code in custom inserter

kumarak
authored and
wizardengineer
committed
[CT] update unit tests for fp types

kumarak
authored and
wizardengineer
committed
[CT] fix mismatch of register type for CTSELECT_I386_GR16 pseudo instruction

kumarak
authored and
wizardengineer
committed
[CT] switch to using class for CTSELECT_I386* and fix formatting

kumarak
authored and
wizardengineer
committed
[CT] Generate more efficient code when fp is from memory

hbrodin
authored and
wizardengineer
committed

Commits on Oct 18, 2025