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[AMDGPU] Reland "Remove redundant s_cmp_lg_* sX, 0" #164201

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Merged
merged 8 commits into from
Oct 22, 2025
Merged

[AMDGPU] Reland "Remove redundant s_cmp_lg_* sX, 0" #164201

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1439b49
Revert "Revert "[AMDGPU] Remove redundant s_cmp_lg_* sX, 0 " (#164116)"
LU-JOHN Oct 19, 2025
5c801f6
SI_PC_ADD_REL_OFFSET does not set SCC = DST!=0
LU-JOHN Oct 20, 2025
706ec85
List suitable opcodes. Negative test for si_pc_add_rel_offset.
LU-JOHN Oct 20, 2025
5c787c0
Remove unused parameter
LU-JOHN Oct 20, 2025
f18fabf
Streamline check for foldable Def
LU-JOHN Oct 21, 2025
8c036ef
Add S_WQM*. Sort opcodes.
LU-JOHN Oct 21, 2025
3518318
Use weak linkage
LU-JOHN Oct 21, 2025
96e16d4
Update llvm/test/CodeGen/AMDGPU/s_cmp_0.ll
LU-JOHN Oct 22, 2025
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55 changes: 37 additions & 18 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -710,26 +710,45 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
}

static bool setsSCCifResultIsNonZero(const MachineInstr &MI) {
if (!MI.findRegisterDefOperand(AMDGPU::SCC, /*TRI=*/nullptr))
return false;
// Compares have no result
if (MI.isCompare())
return false;
switch (MI.getOpcode()) {
default:
case AMDGPU::S_ABS_I32:
case AMDGPU::S_ABSDIFF_I32:
case AMDGPU::S_ASHR_I32:
case AMDGPU::S_ASHR_I64:
case AMDGPU::S_LSHL_B32:
case AMDGPU::S_LSHL_B64:
case AMDGPU::S_LSHR_B32:
case AMDGPU::S_LSHR_B64:
case AMDGPU::S_AND_B32:
case AMDGPU::S_AND_B64:
case AMDGPU::S_OR_B32:
case AMDGPU::S_OR_B64:
case AMDGPU::S_XOR_B32:
case AMDGPU::S_XOR_B64:
case AMDGPU::S_NOT_B32:
case AMDGPU::S_NOT_B64:
case AMDGPU::S_NAND_B32:
case AMDGPU::S_NAND_B64:
case AMDGPU::S_NOR_B32:
case AMDGPU::S_NOR_B64:
case AMDGPU::S_XNOR_B32:
case AMDGPU::S_XNOR_B64:
case AMDGPU::S_ANDN2_B32:
case AMDGPU::S_ANDN2_B64:
case AMDGPU::S_ORN2_B32:
case AMDGPU::S_ORN2_B64:
case AMDGPU::S_BFE_I32:
case AMDGPU::S_BFE_I64:
case AMDGPU::S_BFE_U32:
case AMDGPU::S_BFE_U64:
case AMDGPU::S_BCNT0_I32_B32:
case AMDGPU::S_BCNT0_I32_B64:
case AMDGPU::S_BCNT1_I32_B32:
case AMDGPU::S_BCNT1_I32_B64:
case AMDGPU::S_QUADMASK_B32:
case AMDGPU::S_QUADMASK_B64:
return true;
case AMDGPU::S_ADD_I32:
case AMDGPU::S_ADD_U32:
case AMDGPU::S_ADDC_U32:
case AMDGPU::S_SUB_I32:
case AMDGPU::S_SUB_U32:
case AMDGPU::S_SUBB_U32:
case AMDGPU::S_MIN_I32:
case AMDGPU::S_MIN_U32:
case AMDGPU::S_MAX_I32:
case AMDGPU::S_MAX_U32:
case AMDGPU::S_ADDK_I32:
case AMDGPU::SI_PC_ADD_REL_OFFSET:
default:
return false;
}
}
Expand Down
34 changes: 33 additions & 1 deletion llvm/test/CodeGen/AMDGPU/s_cmp_0.ll
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s

declare i32 @llvm.ctpop.i32(i32)
declare i64 @llvm.ctpop.i64(i64)
Expand Down Expand Up @@ -593,3 +593,35 @@ define amdgpu_ps i32 @not64(i64 inreg %val0) {
%zext = zext i1 %cmp to i32
ret i32 %zext
}


; --------------------------------------------------------------------------------
; Negative tests
; --------------------------------------------------------------------------------

@1 = external dso_local addrspace(4) constant i32

define amdgpu_ps i32 @si_pc_add_rel_offset_must_not_optimize(ptr addrspace(1) %out) {
; CHECK-LABEL: si_pc_add_rel_offset_must_not_optimize:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_getpc_b64 s[0:1]
; CHECK-NEXT: s_add_u32 s0, s0, __unnamed_1@rel32@lo+4
; CHECK-NEXT: s_addc_u32 s1, s1, __unnamed_1@rel32@hi+12
; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0
; CHECK-NEXT: s_cbranch_scc0 .LBB35_2
; CHECK-NEXT: ; %bb.1: ; %endif
; CHECK-NEXT: s_mov_b32 s0, 1
; CHECK-NEXT: s_branch .LBB35_3
; CHECK-NEXT: .LBB35_2: ; %if
; CHECK-NEXT: s_mov_b32 s0, 0
; CHECK-NEXT: s_branch .LBB35_3
; CHECK-NEXT: .LBB35_3:
%cmp = icmp ne ptr addrspace(4) @1, null
br i1 %cmp, label %endif, label %if

if:
ret i32 0

endif:
ret i32 1
}
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