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[RISCV] Use shiftMaskXLen for one of the BCLR patterns. #164206

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Merged
merged 3 commits into from
Oct 21, 2025
+70 −18
Merged

[RISCV] Use shiftMaskXLen for one of the BCLR patterns. #164206

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140b571
Pre-commit test
topperc Oct 20, 2025
d3396a5
[RISCV] Use shiftop<rotl> in one of the BCLR patterns.
topperc Oct 20, 2025
a781cd1
Merge remote-tracking branch 'origin/main' into pr/shiftop-bclr
topperc Oct 20, 2025
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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
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Original file line number Diff line number Diff line change
Expand Up @@ -527,8 +527,8 @@ def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2),
let Predicates = [HasStdExtZbs] in {
def : Pat<(XLenVT (and (not (shl 1, shiftMaskXLen:$rs2)), GPR:$rs1)),
(BCLR GPR:$rs1, shiftMaskXLen:$rs2)>;
def : Pat<(XLenVT (and (rotl -2, (XLenVT GPR:$rs2)), GPR:$rs1)),
(BCLR GPR:$rs1, GPR:$rs2)>;
def : Pat<(XLenVT (and (rotl -2, shiftMaskXLen:$rs2), GPR:$rs1)),
(BCLR GPR:$rs1, shiftMaskXLen:$rs2)>;
def : Pat<(XLenVT (or (shl 1, shiftMaskXLen:$rs2), GPR:$rs1)),
(BSET GPR:$rs1, shiftMaskXLen:$rs2)>;
def : Pat<(XLenVT (xor (shl 1, shiftMaskXLen:$rs2), GPR:$rs1)),
Expand Down
50 changes: 38 additions & 12 deletions llvm/test/CodeGen/RISCV/rv32zbs.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -45,6 +45,32 @@ define i32 @bclr_i32_no_mask(i32 %a, i32 %b) nounwind {
ret i32 %and1
}

define i32 @bclr_i32_mask_multiple(i32 %a, i32 %b, i32 %shamt) nounwind {
; RV32I-LABEL: bclr_i32_mask_multiple:
; RV32I: # %bb.0:
; RV32I-NEXT: li a3, 1
; RV32I-NEXT: sll a2, a3, a2
; RV32I-NEXT: not a3, a2
; RV32I-NEXT: and a0, a3, a0
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
; RV32ZBS-LABEL: bclr_i32_mask_multiple:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bclr a0, a0, a2
; RV32ZBS-NEXT: bset a1, a1, a2
; RV32ZBS-NEXT: add a0, a0, a1
; RV32ZBS-NEXT: ret
%shamt_masked = and i32 %shamt, 63
%shl = shl nuw i32 1, %shamt_masked
%neg = xor i32 %shl, -1
%and = and i32 %neg, %a
%or = or i32 %b, %shl
%c = add i32 %and, %or
ret i32 %c
}

define i64 @bclr_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: bclr_i64:
; RV32I: # %bb.0:
Expand Down Expand Up @@ -301,17 +327,17 @@ define i64 @bext_i64(i64 %a, i64 %b) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a2, 63
; CHECK-NEXT: addi a4, a3, -32
; CHECK-NEXT: bltz a4, .LBB12_2
; CHECK-NEXT: bltz a4, .LBB13_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: srl a0, a1, a3
; CHECK-NEXT: j .LBB12_3
; CHECK-NEXT: .LBB12_2:
; CHECK-NEXT: j .LBB13_3
; CHECK-NEXT: .LBB13_2:
; CHECK-NEXT: srl a0, a0, a2
; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: not a2, a3
; CHECK-NEXT: sll a1, a1, a2
; CHECK-NEXT: or a0, a0, a1
; CHECK-NEXT: .LBB12_3:
; CHECK-NEXT: .LBB13_3:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: li a1, 0
; CHECK-NEXT: ret
Expand Down Expand Up @@ -789,17 +815,17 @@ define i64 @bset_trailing_ones_i64_mask(i64 %a) nounwind {
; CHECK-NEXT: li a3, -1
; CHECK-NEXT: addi a1, a2, -32
; CHECK-NEXT: sll a0, a3, a0
; CHECK-NEXT: bltz a1, .LBB43_2
; CHECK-NEXT: bltz a1, .LBB44_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: sll a2, a3, a2
; CHECK-NEXT: j .LBB43_3
; CHECK-NEXT: .LBB43_2:
; CHECK-NEXT: j .LBB44_3
; CHECK-NEXT: .LBB44_2:
; CHECK-NEXT: not a2, a2
; CHECK-NEXT: lui a3, 524288
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: srl a2, a3, a2
; CHECK-NEXT: or a2, a0, a2
; CHECK-NEXT: .LBB43_3:
; CHECK-NEXT: .LBB44_3:
; CHECK-NEXT: srai a1, a1, 31
; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: not a1, a2
Expand All @@ -817,17 +843,17 @@ define i64 @bset_trailing_ones_i64_no_mask(i64 %a) nounwind {
; CHECK-NEXT: li a1, -1
; CHECK-NEXT: addi a2, a0, -32
; CHECK-NEXT: sll a1, a1, a0
; CHECK-NEXT: bltz a2, .LBB44_2
; CHECK-NEXT: bltz a2, .LBB45_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: j .LBB44_3
; CHECK-NEXT: .LBB44_2:
; CHECK-NEXT: j .LBB45_3
; CHECK-NEXT: .LBB45_2:
; CHECK-NEXT: not a0, a0
; CHECK-NEXT: lui a3, 524288
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: srl a0, a3, a0
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: .LBB44_3:
; CHECK-NEXT: .LBB45_3:
; CHECK-NEXT: srai a2, a2, 31
; CHECK-NEXT: and a2, a2, a1
; CHECK-NEXT: not a1, a0
Expand Down
34 changes: 30 additions & 4 deletions llvm/test/CodeGen/RISCV/rv64zbs.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -110,6 +110,32 @@ define i64 @bclr_i64_no_mask(i64 %a, i64 %b) nounwind {
ret i64 %and1
}

define i64 @bclr_i64_mask_multiple(i64 %a, i64 %b, i64 %shamt) nounwind {
; RV64I-LABEL: bclr_i64_mask_multiple:
; RV64I: # %bb.0:
; RV64I-NEXT: li a3, 1
; RV64I-NEXT: sll a2, a3, a2
; RV64I-NEXT: not a3, a2
; RV64I-NEXT: and a0, a3, a0
; RV64I-NEXT: or a1, a1, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclr_i64_mask_multiple:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclr a0, a0, a2
; RV64ZBS-NEXT: bset a1, a1, a2
; RV64ZBS-NEXT: add a0, a0, a1
; RV64ZBS-NEXT: ret
%shamt_masked = and i64 %shamt, 63
%shl = shl nuw i64 1, %shamt_masked
%neg = xor i64 %shl, -1
%and = and i64 %neg, %a
%or = or i64 %b, %shl
%c = add i64 %and, %or
ret i64 %c
}

define signext i32 @bset_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: bset_i32:
; RV64I: # %bb.0:
Expand Down Expand Up @@ -372,19 +398,19 @@ define void @bext_i32_trunc(i32 signext %0, i32 signext %1) {
; RV64I: # %bb.0:
; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: beqz a0, .LBB19_2
; RV64I-NEXT: beqz a0, .LBB20_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB19_2:
; RV64I-NEXT: .LBB20_2:
; RV64I-NEXT: tail bar
;
; RV64ZBS-LABEL: bext_i32_trunc:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bext a0, a0, a1
; RV64ZBS-NEXT: beqz a0, .LBB19_2
; RV64ZBS-NEXT: beqz a0, .LBB20_2
; RV64ZBS-NEXT: # %bb.1:
; RV64ZBS-NEXT: ret
; RV64ZBS-NEXT: .LBB19_2:
; RV64ZBS-NEXT: .LBB20_2:
; RV64ZBS-NEXT: tail bar
%3 = shl i32 1, %1
%4 = and i32 %3, %0
Expand Down
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