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[AArch64] Widen GPR32 zero cycle zeroing #164244

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Merged
tomershafir merged 1 commit into from
Oct 25, 2025
Merged

[AArch64] Widen GPR32 zero cycle zeroing #164244

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10 changes: 9 additions & 1 deletion llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5116,7 +5116,15 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,

// GPR32 zeroing
if (AArch64::GPR32spRegClass.contains(DestReg) && SrcReg == AArch64::WZR) {
if (Subtarget.hasZeroCycleZeroingGPR32()) {
if (Subtarget.hasZeroCycleZeroingGPR64() &&
!Subtarget.hasZeroCycleZeroingGPR32()) {
MCRegister DestRegX = RI.getMatchingSuperReg(DestReg, AArch64::sub_32,
&AArch64::GPR64spRegClass);
assert(DestRegX.isValid() && "Destination super-reg not valid");
BuildMI(MBB, I, DL, get(AArch64::MOVZXi), DestRegX)
.addImm(0)
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
} else if (Subtarget.hasZeroCycleZeroingGPR32()) {
BuildMI(MBB, I, DL, get(AArch64::MOVZWi), DestReg)
.addImm(0)
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/arm64-copy-phys-zero-reg.mir
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Expand Up @@ -35,7 +35,7 @@ body: |
; CHECK-NOZCZ-GPR32-ZCZ-GPR64-LABEL: name: f0
; CHECK-NOZCZ-GPR32-ZCZ-GPR64: liveins: $x0, $lr
; CHECK-NOZCZ-GPR32-ZCZ-GPR64-NEXT: {{ $}}
; CHECK-NOZCZ-GPR32-ZCZ-GPR64-NEXT: $w0 = ORRWrr $wzr, $wzr
; CHECK-NOZCZ-GPR32-ZCZ-GPR64-NEXT: $x0 = MOVZXi 0, 0
; CHECK-NOZCZ-GPR32-ZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
;
; CHECK-ZCZ-GPR32-ZCZ-GPR64-LABEL: name: f0
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19 changes: 11 additions & 8 deletions llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll
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@@ -1,41 +1,44 @@
; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR
; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR32-NOZCZ-GPR64
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz-gpr32 | FileCheck %s -check-prefixes=ALL,ZCZ-GPR32
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz-gpr64 | FileCheck %s -check-prefixes=ALL,ZCZ-GPR64
; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=generic | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz-gpr64 | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR32-ZCZ-GPR64
; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=generic | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR32-NOZCZ-GPR64
; RUN: llc < %s -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR32-NOZCZ-GPR64
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=kryo | FileCheck %s -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=falkor | FileCheck %s -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64

define i8 @ti8() {
entry:
; ALL-LABEL: ti8:
; NOZCZ-GPR: mov w0, wzr
; NOZCZ-GPR32-NOZCZ-GPR64: mov w0, wzr
; ZCZ-GPR32: mov w0, #0
; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0
ret i8 0
}

define i16 @ti16() {
entry:
; ALL-LABEL: ti16:
; NOZCZ-GPR: mov w0, wzr
; NOZCZ-GPR32-NOZCZ-GPR64: mov w0, wzr
; ZCZ-GPR32: mov w0, #0
; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0
ret i16 0
}

define i32 @ti32() {
entry:
; ALL-LABEL: ti32:
; NOZCZ-GPR: mov w0, wzr
; NOZCZ-GPR32-NOZCZ-GPR64: mov w0, wzr
; ZCZ-GPR32: mov w0, #0
; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0
ret i32 0
}

define i64 @ti64() {
entry:
; ALL-LABEL: ti64:
; NOZCZ-GPR: mov x0, xzr
; NOZCZ-GPR32-NOZCZ-GPR64 mov x0, xzr
; ZCZ-GPR64: mov x0, #0
ret i64 0
}