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9 changes: 9 additions & 0 deletions llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2507,3 +2507,12 @@ void RISCVFrameLowering::inlineStackProbe(MachineFunction &MF,
}
}
}

int RISCVFrameLowering::getInitialCFAOffset(const MachineFunction &MF) const {
return 0;
}

Register
RISCVFrameLowering::getInitialCFARegister(const MachineFunction &MF) const {
return RISCV::X2;
}
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVFrameLowering.h
Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,9 @@ class RISCVFrameLowering : public TargetFrameLowering {
public:
explicit RISCVFrameLowering(const RISCVSubtarget &STI);

int getInitialCFAOffset(const MachineFunction &MF) const override;
Register getInitialCFARegister(const MachineFunction &MF) const override;

void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;

Expand Down
10 changes: 9 additions & 1 deletion llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -103,6 +103,11 @@ static cl::opt<bool>
cl::desc("Enable Machine Pipeliner for RISC-V"),
cl::init(false), cl::Hidden);

static cl::opt<bool> EnableCFIInstrInserter(
"riscv-enable-cfi-instr-inserter",
cl::desc("Enable CFI Instruction Inserter for RISC-V"), cl::init(false),
cl::Hidden);

extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
Expand Down Expand Up @@ -169,7 +174,7 @@ RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
if (TT.isOSFuchsia() && !TT.isArch64Bit())
report_fatal_error("Fuchsia is only supported for 64-bit");

setCFIFixup(true);
setCFIFixup(!EnableCFIInstrInserter);
}

const RISCVSubtarget *
Expand Down Expand Up @@ -576,6 +581,9 @@ void RISCVPassConfig::addPreEmitPass2() {
addPass(createUnpackMachineBundles([&](const MachineFunction &MF) {
return MF.getFunction().getParent()->getModuleFlag("kcfi");
}));

if (EnableCFIInstrInserter)
addPass(createCFIInstrInserter());
}

void RISCVPassConfig::addMachineSSAOptimization() {
Expand Down