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[AMDGPU][MC] Replace shifted registers in CFI instructions #164726

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[AMDGPU][MC] Replace shifted registers in CFI instructions #164726

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4 changes: 4 additions & 0 deletions llvm/include/llvm/CodeGen/MachineFunction.h
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Expand Up @@ -1234,6 +1234,10 @@ class LLVM_ABI MachineFunction {

[[nodiscard]] unsigned addFrameInst(const MCCFIInstruction &Inst);

/// Replace all references to register \param From with register \param To in
/// frame instructions. Note that .cfi_escape instructions will be left as-is.
void replaceFrameInstRegister(Register From, Register To);

/// Returns a reference to a list of symbols immediately following calls to
/// _setjmp in the function. Used to construct the longjmp target table used
/// by Windows Control Flow Guard.
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3 changes: 3 additions & 0 deletions llvm/include/llvm/MC/MCDwarf.h
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Expand Up @@ -837,6 +837,9 @@ class MCCFIInstruction {
return std::get<EscapeFields>(ExtraFields).Comment;
}
SMLoc getLoc() const { return Loc; }

/// Replaces in place all references to FromReg with ToReg.
void replaceRegister(unsigned FromReg, unsigned ToReg);
};

struct MCDwarfFrameInfo {
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10 changes: 10 additions & 0 deletions llvm/lib/CodeGen/MachineFunction.cpp
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Expand Up @@ -336,6 +336,16 @@ MachineFunction::addFrameInst(const MCCFIInstruction &Inst) {
return FrameInstructions.size() - 1;
}

void MachineFunction::replaceFrameInstRegister(Register FromReg,
Register ToReg) {
const MCRegisterInfo *MCRI = Ctx.getRegisterInfo();
unsigned DwarfFromReg = MCRI->getDwarfRegNum(FromReg, false);
unsigned DwarfToReg = MCRI->getDwarfRegNum(ToReg, false);

for (MCCFIInstruction &Inst : FrameInstructions)
Inst.replaceRegister(DwarfFromReg, DwarfToReg);
}

/// This discards all of the MachineBasicBlock numbers and recomputes them.
/// This guarantees that the MBB numbers are sequential, dense, and match the
/// ordering of the blocks within the function. If a specific MachineBasicBlock
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33 changes: 33 additions & 0 deletions llvm/lib/MC/MCDwarf.cpp
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Expand Up @@ -1292,6 +1292,39 @@ void MCGenDwarfLabelEntry::Make(MCSymbol *Symbol, MCStreamer *MCOS,
MCGenDwarfLabelEntry(Name, FileNumber, LineNumber, Label));
}

void MCCFIInstruction::replaceRegister(unsigned FromReg, unsigned ToReg) {
auto ReplaceReg = [=](unsigned &Reg) {
if (Reg == FromReg)
Reg = ToReg;
};
auto Visitor = makeVisitor(
[=](CommonFields &F) {
ReplaceReg(F.Register);
ReplaceReg(F.Register2);
},
[](EscapeFields &) {}, [](LabelFields &) {},
[=](RegisterPairFields &F) {
ReplaceReg(F.Register);
ReplaceReg(F.Reg1);
ReplaceReg(F.Reg2);
},
[=](VectorRegistersFields &F) {
ReplaceReg(F.Register);
for (auto &VRL : F.VectorRegisters)
ReplaceReg(VRL.Register);
},
[=](VectorOffsetFields &F) {
ReplaceReg(F.Register);
ReplaceReg(F.MaskRegister);
},
[=](VectorRegisterMaskFields &F) {
ReplaceReg(F.Register);
ReplaceReg(F.SpillRegister);
ReplaceReg(F.MaskRegister);
});
std::visit(Visitor, ExtraFields);
}

static int getDataAlignmentFactor(MCStreamer &streamer) {
MCContext &context = streamer.getContext();
const MCAsmInfo *asmInfo = context.getAsmInfo();
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3 changes: 3 additions & 0 deletions llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
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Expand Up @@ -386,6 +386,9 @@ void SIMachineFunctionInfo::shiftWwmVGPRsToLowestRange(
if (RegItr != SpillPhysVGPRs.end()) {
unsigned Idx = std::distance(SpillPhysVGPRs.begin(), RegItr);
SpillPhysVGPRs[Idx] = NewReg;

// For replacing registers used in the CFI instructions.
MF.replaceFrameInstRegister(Reg, NewReg);
}

// The generic `determineCalleeSaves` might have set the old register if it
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AMDGPU/debug-frame.ll
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Expand Up @@ -2449,7 +2449,7 @@ define hidden void @func_call_clobber() #0 {
; GFX900-NEXT: v_writelane_b32 v40, s30, 0
; GFX900-NEXT: s_addk_i32 s32, 0x400
; GFX900-NEXT: v_writelane_b32 v40, s31, 1
; GFX900-NEXT: .cfi_llvm_vector_registers 16, 2815, 0, 32, 2815, 1, 32
; GFX900-NEXT: .cfi_llvm_vector_registers 16, 2600, 0, 32, 2600, 1, 32
; GFX900-NEXT: s_getpc_b64 s[16:17]
; GFX900-NEXT: s_add_u32 s16, s16, ex@rel32@lo+4
; GFX900-NEXT: s_addc_u32 s17, s17, ex@rel32@hi+12
Expand Down Expand Up @@ -2723,7 +2723,7 @@ define hidden void @func_call_clobber() #0 {
; GFX90A-V2A-DIS-NEXT: v_writelane_b32 v40, s30, 0
; GFX90A-V2A-DIS-NEXT: s_addk_i32 s32, 0x400
; GFX90A-V2A-DIS-NEXT: v_writelane_b32 v40, s31, 1
; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_registers 16, 2815, 0, 32, 2815, 1, 32
; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_registers 16, 2600, 0, 32, 2600, 1, 32
; GFX90A-V2A-DIS-NEXT: s_getpc_b64 s[16:17]
; GFX90A-V2A-DIS-NEXT: s_add_u32 s16, s16, ex@rel32@lo+4
; GFX90A-V2A-DIS-NEXT: s_addc_u32 s17, s17, ex@rel32@hi+12
Expand Down Expand Up @@ -2997,7 +2997,7 @@ define hidden void @func_call_clobber() #0 {
; GFX90A-V2A-EN-NEXT: v_writelane_b32 v40, s30, 0
; GFX90A-V2A-EN-NEXT: s_addk_i32 s32, 0x400
; GFX90A-V2A-EN-NEXT: v_writelane_b32 v40, s31, 1
; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_registers 16, 2815, 0, 32, 2815, 1, 32
; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_registers 16, 2600, 0, 32, 2600, 1, 32
; GFX90A-V2A-EN-NEXT: s_getpc_b64 s[16:17]
; GFX90A-V2A-EN-NEXT: s_add_u32 s16, s16, ex@rel32@lo+4
; GFX90A-V2A-EN-NEXT: s_addc_u32 s17, s17, ex@rel32@hi+12
Expand Down Expand Up @@ -3240,7 +3240,7 @@ define hidden void @func_call_clobber() #0 {
; WAVE32-NEXT: v_writelane_b32 v40, s30, 0
; WAVE32-NEXT: s_addk_i32 s32, 0x200
; WAVE32-NEXT: v_writelane_b32 v40, s31, 1
; WAVE32-NEXT: .cfi_llvm_vector_registers 16, 1791, 0, 32, 1791, 1, 32
; WAVE32-NEXT: .cfi_llvm_vector_registers 16, 1576, 0, 32, 1576, 1, 32
; WAVE32-NEXT: s_getpc_b64 s[16:17]
; WAVE32-NEXT: s_add_u32 s16, s16, ex@rel32@lo+4
; WAVE32-NEXT: s_addc_u32 s17, s17, ex@rel32@hi+12
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30 changes: 15 additions & 15 deletions llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
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Expand Up @@ -493,36 +493,36 @@ define weak_odr void @test(i32 %0) !dbg !34 {
; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; CHECK-NEXT: .cfi_llvm_vector_offset 2600, 32, 17, 64, 0
; CHECK-NEXT: v_writelane_b32 v41, s34, 0
; CHECK-NEXT: .cfi_llvm_vector_registers 66, 2622, 0, 32
; CHECK-NEXT: .cfi_llvm_vector_registers 66, 2601, 0, 32
; CHECK-NEXT: v_writelane_b32 v41, s35, 1
; CHECK-NEXT: .cfi_llvm_vector_registers 67, 2622, 1, 32
; CHECK-NEXT: .cfi_llvm_vector_registers 67, 2601, 1, 32
; CHECK-NEXT: v_writelane_b32 v41, s36, 2
; CHECK-NEXT: .cfi_llvm_vector_registers 68, 2622, 2, 32
; CHECK-NEXT: .cfi_llvm_vector_registers 68, 2601, 2, 32
; CHECK-NEXT: v_writelane_b32 v41, s37, 3
; CHECK-NEXT: .cfi_llvm_vector_registers 69, 2622, 3, 32
; CHECK-NEXT: .cfi_llvm_vector_registers 69, 2601, 3, 32
; CHECK-NEXT: v_writelane_b32 v41, s38, 4
; CHECK-NEXT: .cfi_llvm_vector_registers 70, 2622, 4, 32
; CHECK-NEXT: .cfi_llvm_vector_registers 70, 2601, 4, 32
; CHECK-NEXT: v_writelane_b32 v41, s39, 5
; CHECK-NEXT: .cfi_llvm_vector_registers 71, 2622, 5, 32
; CHECK-NEXT: .cfi_llvm_vector_registers 71, 2601, 5, 32
; CHECK-NEXT: v_writelane_b32 v41, s48, 6
; CHECK-NEXT: .cfi_llvm_vector_registers 80, 2622, 6, 32
; CHECK-NEXT: .cfi_llvm_vector_registers 80, 2601, 6, 32
; CHECK-NEXT: v_writelane_b32 v41, s49, 7
; CHECK-NEXT: .cfi_llvm_vector_registers 81, 2622, 7, 32
; CHECK-NEXT: .cfi_llvm_vector_registers 81, 2601, 7, 32
; CHECK-NEXT: v_writelane_b32 v41, s50, 8
; CHECK-NEXT: .cfi_llvm_vector_registers 82, 2622, 8, 32
; CHECK-NEXT: .cfi_llvm_vector_registers 82, 2601, 8, 32
; CHECK-NEXT: v_writelane_b32 v41, s51, 9
; CHECK-NEXT: .cfi_llvm_vector_registers 83, 2622, 9, 32
; CHECK-NEXT: .cfi_llvm_vector_registers 83, 2601, 9, 32
; CHECK-NEXT: v_writelane_b32 v41, s52, 10
; CHECK-NEXT: .cfi_llvm_vector_registers 84, 2622, 10, 32
; CHECK-NEXT: .cfi_llvm_vector_registers 84, 2601, 10, 32
; CHECK-NEXT: v_writelane_b32 v41, s53, 11
; CHECK-NEXT: .cfi_llvm_vector_registers 85, 2622, 11, 32
; CHECK-NEXT: .cfi_llvm_vector_registers 85, 2601, 11, 32
; CHECK-NEXT: v_writelane_b32 v41, s54, 12
; CHECK-NEXT: .cfi_llvm_vector_registers 86, 2622, 12, 32
; CHECK-NEXT: .cfi_llvm_vector_registers 86, 2601, 12, 32
; CHECK-NEXT: v_writelane_b32 v41, s55, 13
; CHECK-NEXT: .cfi_llvm_vector_registers 87, 2622, 13, 32
; CHECK-NEXT: .cfi_llvm_vector_registers 87, 2601, 13, 32
; CHECK-NEXT: v_writelane_b32 v41, s30, 14
; CHECK-NEXT: v_writelane_b32 v41, s31, 15
; CHECK-NEXT: .cfi_llvm_vector_registers 16, 2622, 14, 32, 2622, 15, 32
; CHECK-NEXT: .cfi_llvm_vector_registers 16, 2601, 14, 32, 2601, 15, 32
; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5]
; CHECK-NEXT: ;DEBUG_VALUE: dummy:dummy <- undef
; CHECK-NEXT: .Ltmp0:
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll
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Expand Up @@ -230,7 +230,7 @@ define fastcc i32 @foo() {
; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr30, 0, $vgpr40, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31
; CHECK-NEXT: $sgpr32 = frame-setup S_ADDK_I32 $sgpr32, 512, implicit-def dead $scc
; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr31, 1, $vgpr40, implicit $sgpr30_sgpr31
; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr127, 0, 32, $vgpr127, 1, 32
; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr40, 0, 32, $vgpr40, 1, 32
; CHECK-NEXT: BUNDLE implicit-def $sgpr16_sgpr17, implicit-def $sgpr16, implicit-def $scc, implicit-def $sgpr17 {
; CHECK-NEXT: $sgpr16_sgpr17 = S_GETPC_B64
; CHECK-NEXT: $sgpr16 = S_ADD_U32 internal $sgpr16, target-flags(amdgpu-gotprel32-lo) @bar + 4, implicit-def $scc
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
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Expand Up @@ -233,7 +233,7 @@ define hidden void @_ZL3barv() #0 !dbg !1644 {
; CHECK-NEXT: s_add_i32 s32, s32, 0x400
; CHECK-NEXT: v_writelane_b32 v40, s30, 0
; CHECK-NEXT: v_writelane_b32 v40, s31, 1
; CHECK-NEXT: .cfi_llvm_vector_registers 16, 2623, 0, 32, 2623, 1, 32
; CHECK-NEXT: .cfi_llvm_vector_registers 16, 2600, 0, 32, 2600, 1, 32
; CHECK-NEXT: .Ltmp0:
; CHECK-NEXT: .loc 0 31 3 prologue_end ; lane-info.cpp:31:3
; CHECK-NEXT: s_getpc_b64 s[16:17]
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