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[AMDGPU] Generate s_absdiff_i32 #164835

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Merged
merged 3 commits into from
Oct 27, 2025
Merged

[AMDGPU] Generate s_absdiff_i32 #164835

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a371ba3
Generate s_absdiff_i32
LU-JOHN Oct 21, 2025
81b0703
Remove unnecessary braces
LU-JOHN Oct 23, 2025
6720b3d
Add absdiff test variations
LU-JOHN Oct 24, 2025
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8 changes: 5 additions & 3 deletions llvm/lib/Target/AMDGPU/SOPInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -838,9 +838,11 @@ def S_CBRANCH_G_FORK : SOP2_Pseudo <
let SubtargetPredicate = isGFX6GFX7GFX8GFX9;
}

let Defs = [SCC] in {
def S_ABSDIFF_I32 : SOP2_32 <"s_absdiff_i32">;
} // End Defs = [SCC]
let isCommutable = 1, Defs = [SCC] in {
def S_ABSDIFF_I32 : SOP2_32 <"s_absdiff_i32",
[(set i32:$sdst, (UniformUnaryFrag<abs> (sub_oneuse i32:$src0, i32:$src1)))]
>;
} // End isCommutable = 1, Defs = [SCC]

let SubtargetPredicate = isGFX8GFX9 in {
def S_RFE_RESTORE_B64 : SOP2_Pseudo <
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12 changes: 12 additions & 0 deletions llvm/test/CodeGen/AMDGPU/absdiff.ll
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@@ -0,0 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck %s

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@arsenm arsenm Oct 24, 2025

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Also test 16-bit promoted case

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@LU-JOHN LU-JOHN Oct 24, 2025 •
edited
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Added 16-bit test case.

define amdgpu_ps i32 @absdiff_v1(i32 inreg %arg, i32 inreg %arg2) {
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@arsenm arsenm Oct 24, 2025

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Test vectors

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@LU-JOHN LU-JOHN Oct 24, 2025

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Tested <2 x i32> and <4 x i32>

; CHECK-LABEL: absdiff_v1:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_absdiff_i32 s0, s0, s1
; CHECK-NEXT: ; return to shader part epilog
%diff = sub i32 %arg, %arg2
%res = call i32 @llvm.abs.i32(i32 %diff, i1 false)
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@arsenm arsenm Oct 24, 2025

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Also test with true?

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@LU-JOHN LU-JOHN Oct 24, 2025

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Added test with true variant.

ret i32 %res
}
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@arsenm arsenm Oct 24, 2025

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Negative test for the multi use case?

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@LU-JOHN LU-JOHN Oct 24, 2025

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Added negative test for multi-use case.

25 changes: 20 additions & 5 deletions llvm/test/CodeGen/AMDGPU/s_cmp_0.ll
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Expand Up @@ -110,6 +110,21 @@ define amdgpu_ps i32 @abs32(i32 inreg %val0) {
ret i32 %zext
}

define amdgpu_ps i32 @absdiff32(i32 inreg %val0, i32 inreg %val1) {
; CHECK-LABEL: absdiff32:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_absdiff_i32 s0, s0, s1
; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
Comment on lines +117 to +119
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@jayfoad jayfoad Oct 23, 2025

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Codegen is terrible here, but that's not your fault. Should be:

Suggested change
; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
; CHECK-NEXT: s_cselect_b32 s0, 1, 0

; CHECK-NEXT: ; return to shader part epilog
%diff = sub i32 %val0, %val1
%result = call i32 @llvm.abs.i32(i32 %diff, i1 false)
%cmp = icmp ne i32 %result, 0
%zext = zext i1 %cmp to i32
ret i32 %zext
}

define amdgpu_ps i32 @and32(i32 inreg %val0, i32 inreg %val1) {
; CHECK-LABEL: and32:
; CHECK: ; %bb.0:
Expand Down Expand Up @@ -608,14 +623,14 @@ define amdgpu_ps i32 @si_pc_add_rel_offset_must_not_optimize() {
; CHECK-NEXT: s_add_u32 s0, s0, __unnamed_1@rel32@lo+4
; CHECK-NEXT: s_addc_u32 s1, s1, __unnamed_1@rel32@hi+12
; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0
; CHECK-NEXT: s_cbranch_scc0 .LBB35_2
; CHECK-NEXT: s_cbranch_scc0 .LBB36_2
; CHECK-NEXT: ; %bb.1: ; %endif
; CHECK-NEXT: s_mov_b32 s0, 1
; CHECK-NEXT: s_branch .LBB35_3
; CHECK-NEXT: .LBB35_2: ; %if
; CHECK-NEXT: s_branch .LBB36_3
; CHECK-NEXT: .LBB36_2: ; %if
; CHECK-NEXT: s_mov_b32 s0, 0
; CHECK-NEXT: s_branch .LBB35_3
; CHECK-NEXT: .LBB35_3:
; CHECK-NEXT: s_branch .LBB36_3
; CHECK-NEXT: .LBB36_3:
%cmp = icmp ne ptr addrspace(4) @1, null
br i1 %cmp, label %endif, label %if

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