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[X86][ISel] Improve VPTERNLOG matching for negated logic trees #164863

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Merged
merged 5 commits into from
Oct 25, 2025
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[X86][ISel] Improve VPTERNLOG matching for negated logic trees #164863

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f66a0cb
[X86][ISel] Improve VPTERNLOG matching for negated logic trees
yichi170 Oct 23, 2025
0cc7cd9
clang-format
yichi170 Oct 23, 2025
6aafdb0
remove unused variable
yichi170 Oct 23, 2025
9092c7e
address some comments
yichi170 Oct 24, 2025
97201e7
address comments
yichi170 Oct 24, 2025
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36 changes: 32 additions & 4 deletions llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4721,9 +4721,6 @@ bool X86DAGToDAGISel::tryVPTERNLOG(SDNode *N) {
if (!(Subtarget->hasVLX() || NVT.is512BitVector()))
return false;

SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);

auto getFoldableLogicOp = [](SDValue Op) {
// Peek through single use bitcast.
if (Op.getOpcode() == ISD::BITCAST && Op.hasOneUse())
Expand All @@ -4740,6 +4737,34 @@ bool X86DAGToDAGISel::tryVPTERNLOG(SDNode *N) {
return SDValue();
};

// Identify and (optionally) peel an outer NOT that wraps a pure logic tree
auto tryPeelOuterNotWrappingLogic = [&](SDNode *Op) {
if (Op->getOpcode() == ISD::XOR && Op->hasOneUse() &&
ISD::isBuildVectorAllOnes(Op->getOperand(1).getNode())) {
SDValue InnerOp = Op->getOperand(0);

if (!getFoldableLogicOp(InnerOp)) {
return SDValue();
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@RKSimon RKSimon Nov 3, 2025

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@yichi170 Should this be:

SDValue InnerOp = getFoldableLogicOp(Op->getOperand(0));
if (!InnerOp)
  return SDValue();

getFoldableLogicOp might peek through a bitcast so the original InnerOp might not be a logic binop

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@yichi170 yichi170 Nov 3, 2025 •
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Yes, you're right. Thanks for pointing it out! Should I submit another PR to fix it?

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@RKSimon RKSimon Nov 5, 2025

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yes please - I've managed to get a test case to crash here, but you might have ideas for a better one:

define <32 x i8> @crashme(<32 x i8> %a0) {
  %cmp = icmp ne <32 x i8> %a0, zeroinitializer
  %sext = sext <32 x i1> %cmp to <32 x i8>
  %xor = xor <32 x i8> %a0, %sext
  %shuffle = shufflevector <32 x i8> %xor, <32 x i8> zeroinitializer, <32 x i32> <i32 3, i32 1, i32 3, i32 2, i32 3, i32 2, i32 0, i32 1, i32 0, i32 1, i32 1, i32 2, i32 3, i32 3, i32 1, i32 3, i32 1, i32 3, i32 2, i32 2, i32 0, i32 3, i32 1, i32 1, i32 3, i32 0, i32 0, i32 3, i32 3, i32 0, i32 0, i32 0>
  ret <32 x i8> %shuffle
}

}

SDValue InnerN0 = InnerOp.getOperand(0);
SDValue InnerN1 = InnerOp.getOperand(1);
if (getFoldableLogicOp(InnerN1) || getFoldableLogicOp(InnerN0))
return InnerOp;
}
return SDValue();
};

bool PeeledOuterNot = false;
SDNode *OriN = N;
if (SDValue InnerOp = tryPeelOuterNotWrappingLogic(N)) {
PeeledOuterNot = true;
N = InnerOp.getNode();
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@phoebewang phoebewang Oct 24, 2025

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Suggested change
N = InnerOp.getNode();
ParentA = InnerOp.getNode();

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@phoebewang phoebewang Oct 24, 2025

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Unfortunately, we still need N in line 4813...

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@yichi170 yichi170 Oct 24, 2025

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If we peel the not out, the immediate (Imm) should be computed using the inner node (InnerOp), since the negation will be applied afterward. Therefore, we should not update this line here.

}

SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);

SDValue A, FoldableOp;
if ((FoldableOp = getFoldableLogicOp(N1))) {
A = N0;
Expand Down Expand Up @@ -4798,7 +4823,10 @@ bool X86DAGToDAGISel::tryVPTERNLOG(SDNode *N) {
case ISD::XOR: Imm ^= TernlogMagicA; break;
}

return matchVPTERNLOG(N, ParentA, ParentB, ParentC, A, B, C, Imm);
if (PeeledOuterNot)
Imm = ~Imm;

return matchVPTERNLOG(OriN, ParentA, ParentB, ParentC, A, B, C, Imm);
}

/// If the high bits of an 'and' operand are known zero, try setting the
Expand Down
13 changes: 13 additions & 0 deletions llvm/test/CodeGen/X86/issue163738.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512f,+avx512vl | FileCheck %s --check-prefixes=CHECK

define <8 x i64> @foo(<8 x i64> %a, <8 x i64> %b, <8 x i64> %c) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: vpternlogq {{.*#+}} zmm0 = ~(zmm0 | zmm2 | zmm1)
; CHECK-NEXT: retq
%and.demorgan = or <8 x i64> %b, %a
%and3.demorgan = or <8 x i64> %and.demorgan, %c
%and3 = xor <8 x i64> %and3.demorgan, splat (i64 -1)
ret <8 x i64> %and3
}