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[RISCV] Rename RISCVISD::ABSW->NEGW_MAX. NFC #164909

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Merged
merged 1 commit into from
Oct 23, 2025
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[RISCV] Rename RISCVISD::ABSW->NEGW_MAX. NFC #164909

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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -14797,7 +14797,7 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
// to NEGW+MAX here requires a Freeze which breaks ComputeNumSignBits.
SDValue Src = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64,
N->getOperand(0));
SDValue Abs = DAG.getNode(RISCVISD::ABSW, DL, MVT::i64, Src);
SDValue Abs = DAG.getNode(RISCVISD::NEGW_MAX, DL, MVT::i64, Src);
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Abs));
return;
}
Expand Down Expand Up @@ -21813,7 +21813,7 @@ unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(
// Output is either all zero or operand 0. We can propagate sign bit count
// from operand 0.
return DAG.ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
case RISCVISD::ABSW: {
case RISCVISD::NEGW_MAX: {
// We expand this at isel to negw+max. The result will have 33 sign bits
// if the input has at least 33 sign bits.
unsigned Tmp =
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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
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Expand Up @@ -51,7 +51,7 @@ def riscv_zip : RVSDNode<"ZIP", SDTIntUnaryOp>;
def riscv_unzip : RVSDNode<"UNZIP", SDTIntUnaryOp>;

// RV64IZbb absolute value for i32. Expanded to (max (negw X), X) during isel.
def riscv_absw : RVSDNode<"ABSW", SDTIntUnaryOp>;
def riscv_negw_max : RVSDNode<"NEGW_MAX", SDTIntUnaryOp>;

// Scalar cryptography
def riscv_clmul : RVSDNode<"CLMUL", SDTIntBinOp>;
Expand Down Expand Up @@ -610,7 +610,7 @@ def : PatGpr<riscv_clzw, CLZW>;
def : PatGpr<riscv_ctzw, CTZW>;
def : Pat<(i64 (ctpop (i64 (zexti32 (i64 GPR:$rs1))))), (CPOPW GPR:$rs1)>;

def : Pat<(i64 (riscv_absw GPR:$rs1)),
def : Pat<(i64 (riscv_negw_max GPR:$rs1)),
(MAX GPR:$rs1, (XLenVT (SUBW (XLenVT X0), GPR:$rs1)))>;
} // Predicates = [HasStdExtZbb, IsRV64]

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