Skip to content

[AArch64][llvm] Add support for Permission Overlays Extension 2 (FEAT_S1POE2) #164912

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 2 commits into
base: main
Choose a base branch
from
+4,020 −6
Open

[AArch64][llvm] Add support for Permission Overlays Extension 2 (FEAT_S1POE2) #164912

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
715ea15
[AArch64][llvm] Add support for Permission Overlays Extension 2 (FEAT…
jthackray Sep 2, 2025
b3a019f
fixup! [AArch64][llvm] Add support for Permission Overlays Extension …
jthackray Nov 3, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
15 changes: 15 additions & 0 deletions clang/test/Driver/aarch64-vfat.c
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,15 @@
// ===== Features supported on aarch64 =====

// FAT features (Future Architecture Technologies)

// RUN: %clang -target aarch64 -march=armv9.7a+poe2 -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-POE2 %s
// RUN: %clang -target aarch64 -march=armv9.7-a+poe2 -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-POE2 %s
// VFAT-POE2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+poe2"

// RUN: %clang -target aarch64 -march=armv9.7a+tev -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-TEV %s
// RUN: %clang -target aarch64 -march=armv9.7-a+tev -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-TEV %s
// VFAT-TEV: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+tev"

// RUN: %clang -target aarch64 -march=armv9.7a+btie -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-BTIE %s
// RUN: %clang -target aarch64 -march=armv9.7-a+btie -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-BTIE %s
// VFAT-BTIE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+btie"
3 changes: 3 additions & 0 deletions clang/test/Driver/print-supported-extensions-aarch64.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,7 @@
// CHECK-NEXT: bf16 FEAT_BF16 Enable BFloat16 Extension
// CHECK-NEXT: brbe FEAT_BRBE Enable Branch Record Buffer Extension
// CHECK-NEXT: bti FEAT_BTI Enable Branch Target Identification
// CHECK-NEXT: btie FEAT_BTIE Enable Enhanced Branch Target Identification extension
// CHECK-NEXT: cmh FEAT_CMH Enable Armv9.7-A Contention Management Hints
// CHECK-NEXT: cmpbr FEAT_CMPBR Enable Armv9.6-A base compare and branch instructions
// CHECK-NEXT: fcma FEAT_FCMA Enable Armv8.3-A Floating-point complex number support
Expand Down Expand Up @@ -58,6 +59,7 @@
// CHECK-NEXT: pauth-lr FEAT_PAuth_LR Enable Armv9.5-A PAC enhancements
// CHECK-NEXT: pcdphint FEAT_PCDPHINT Enable Armv9.6-A Producer Consumer Data Placement hints
// CHECK-NEXT: pmuv3 FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: poe2 FEAT_S1POE2 Enable Stage 1 Permission Overlays Extension 2 instructions
// CHECK-NEXT: pops FEAT_PoPS Enable Armv9.6-A Point Of Physical Storage (PoPS) DC instructions
// CHECK-NEXT: predres FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
// CHECK-NEXT: rng FEAT_RNG Enable Random Number generation instructions
Expand Down Expand Up @@ -112,6 +114,7 @@
// CHECK-NEXT: sve2p1 FEAT_SVE2p1 Enable Scalable Vector Extension 2.1 instructions
// CHECK-NEXT: sve2p2 FEAT_SVE2p2 Enable Armv9.6-A Scalable Vector Extension 2.2 instructions
// CHECK-NEXT: sve2p3 FEAT_SVE2p3 Enable Armv9.7-A Scalable Vector Extension 2.3 instructions
// CHECK-NEXT: tev FEAT_TEV Enable TIndex Exception-like Vector instructions
// CHECK-NEXT: the FEAT_THE Enable Armv8.9-A Translation Hardening Extension
// CHECK-NEXT: tlbid FEAT_TLBID Enable Armv9.7-A TLBI Domains extension
// CHECK-NEXT: tlbiw FEAT_TLBIW Enable Armv9.5-A TLBI VMALL for Dirty State
Expand Down
13 changes: 13 additions & 0 deletions llvm/lib/Target/AArch64/AArch64Features.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -625,6 +625,19 @@ def FeatureF16F32DOT : ExtensionWithMArch<"f16f32dot", "F16F32DOT", "FEAT_F16F32
def FeatureF16F32MM : ExtensionWithMArch<"f16f32mm", "F16F32MM", "FEAT_F16F32MM",
"Enable Armv9.7-A Advanced SIMD half-precision matrix multiply-accumulate to single-precision", [FeatureNEON, FeatureFullFP16]>;

//===----------------------------------------------------------------------===//
// Future Architecture Technologies
//===----------------------------------------------------------------------===//

def FeatureBTIE: ExtensionWithMArch<"btie", "BTIE", "FEAT_BTIE",
"Enable Enhanced Branch Target Identification extension">;

def FeatureS1POE2: ExtensionWithMArch<"poe2", "POE2", "FEAT_S1POE2",
"Enable Stage 1 Permission Overlays Extension 2 instructions", [FeatureBTIE]>;
Copy link
Contributor

@CarolineConcatto CarolineConcatto Oct 31, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I believe POE should not depend on FeatureBTIE.

Copy link
Contributor Author

@jthackray jthackray Oct 31, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

The POE2 spec says:

"If FEAT_S1POE2 is implemented then FEAT_BTIE is also implemented."

but I don't think our sync with GNU recorded this; I think I only spotted this later. I will check again next week. I think if POE2 is enabled, we should also enable +btie, although I don't think GNU want a flag for +btie. We'll sort these nits out next week.


def FeatureTEV: ExtensionWithMArch<"tev", "TEV", "FEAT_TEV",
"Enable TIndex Exception-like Vector instructions">;

//===----------------------------------------------------------------------===//
// Other Features
//===----------------------------------------------------------------------===//
Expand Down
98 changes: 98 additions & 0 deletions llvm/lib/Target/AArch64/AArch64InstrFormats.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1909,6 +1909,21 @@ def CMHPriorityHint_op : Operand<i32> {
}];
}

def TIndexHintOperand : AsmOperandClass {
let Name = "TIndexHint";
let ParserMethod = "tryParseTIndexHint";
}

def TIndexhint_op : Operand<i32> {
let ParserMatchClass = TIndexHintOperand;
let PrintMethod = "printTIndexHintOp";
let MCOperandPredicate = [{
if (!MCOp.isImm())
return false;
return AArch64TIndexHint::lookupTIndexByEncoding(MCOp.getImm()) != nullptr;
}];
}

class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
"mrs", "\t$Rt, $systemreg"> {
bits<16> systemreg;
Expand Down Expand Up @@ -13338,3 +13353,86 @@ class STCPHInst<string asm> : I<
let Inst{7-5} = 0b100;
let Inst{4-0} = 0b11111;
}

//---
// Permission Overlays Extension 2 (FEAT_S1POE2)
//---

class TCHANGERegInst<string asm, bit isB> : I<
(outs GPR64:$Xd),
(ins GPR64:$Xn, TIndexhint_op:$nb),
asm, "\t$Xd, $Xn, $nb", "", []>, Sched<[]> {
bits<5> Xd;
bits<5> Xn;
bits<1> nb;
let Inst{31-19} = 0b1101010110000;
let Inst{18} = isB;
let Inst{17} = nb;
let Inst{16-10} = 0b0000000;
let Inst{9-5} = Xn;
let Inst{4-0} = Xd;
}

class TCHANGEImmInst<string asm, bit isB> : I<
(outs GPR64:$Xd),
(ins imm0_127:$imm, TIndexhint_op:$nb),
asm, "\t$Xd, $imm, $nb", "", []>, Sched<[]> {
bits<5> Xd;
bits<7> imm;
bits<1> nb;
let Inst{31-19} = 0b1101010110010;
let Inst{18} = isB;
let Inst{17} = nb;
let Inst{16-12} = 0b00000;
let Inst{11-5} = imm;
let Inst{4-0} = Xd;
}

class TENTERInst<string asm> : I<
(outs),
(ins imm0_127:$imm, TIndexhint_op:$nb),
asm, "\t$imm, $nb", "", []>, Sched<[]> {
bits<7> imm;
bits<1> nb;
let Inst{31-20} = 0b110101001110;
let Inst{19-18} = 0b00;
let Inst{17} = nb;
let Inst{16-12} = 0b00000;
let Inst{11-5} = imm;
let Inst{4-0} = 0b00000;
}

class TEXITInst<string asm> : I<
(outs),
(ins TIndexhint_op:$nb),
asm, "\t$nb", "", []>, Sched<[]> {
bits<1> nb;
let Inst{31-13} = 0b1101011011111111000;
let Inst{12-11} = 0b00;
let Inst{10} = nb;
let Inst{9-0} = 0b1111100000;
}


multiclass TCHANGEReg<string asm , bit isB> {
def NAME : TCHANGERegInst<asm, isB>;
def : InstAlias<asm # "\t$Xd, $Xn",
(!cast<Instruction>(NAME) GPR64:$Xd, GPR64:$Xn, 0), 1>;
}

multiclass TCHANGEImm<string asm, bit isB> {
def NAME : TCHANGEImmInst<asm, isB>;
def : InstAlias<asm # "\t$Xd, $Xn",
(!cast<Instruction>(NAME) GPR64:$Xd, imm0_127:$Xn, 0), 1>;
}

multiclass TENTER<string asm> {
def NAME : TENTERInst<asm>;
def : InstAlias<asm # "\t$imm",
(!cast<Instruction>(NAME) imm0_127:$imm, 0), 1>;
}

multiclass TEXIT<string asm> {
def NAME : TEXITInst<asm>;
def : InstAlias<asm, (!cast<Instruction>(NAME) 0), 1>;
}
27 changes: 27 additions & 0 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -346,6 +346,8 @@ def HasCCDP : Predicate<"Subtarget->hasCCDP()">,
AssemblerPredicateWithAll<(all_of FeatureCacheDeepPersist), "ccdp">;
def HasBTI : Predicate<"Subtarget->hasBTI()">,
AssemblerPredicateWithAll<(all_of FeatureBranchTargetId), "bti">;
def HasBTIE : Predicate<"Subtarget->hasBTIE()">,
AssemblerPredicateWithAll<(all_of FeatureBTIE), "btie">;
def HasMTE : Predicate<"Subtarget->hasMTE()">,
AssemblerPredicateWithAll<(all_of FeatureMTE), "mte">;
def HasTME : Predicate<"Subtarget->hasTME()">,
Expand Down Expand Up @@ -405,6 +407,10 @@ def HasMTETC : Predicate<"Subtarget->hasMTETC()">,
AssemblerPredicateWithAll<(all_of FeatureMTETC), "mtetc">;
def HasGCIE : Predicate<"Subtarget->hasGCIE()">,
AssemblerPredicateWithAll<(all_of FeatureGCIE), "gcie">;
def HasS1POE2 : Predicate<"Subtarget->hasS1POE2()">,
AssemblerPredicateWithAll<(all_of FeatureS1POE2), "poe2">;
def HasTEV : Predicate<"Subtarget->hasTEV()">,
AssemblerPredicateWithAll<(all_of FeatureTEV), "tev">;
def IsLE : Predicate<"Subtarget->isLittleEndian()">;
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
def IsWindows : Predicate<"Subtarget->isTargetWindows()">;
Expand Down Expand Up @@ -1540,6 +1546,7 @@ let Predicates = [HasPCDPHINT] in {
// should not emit these mnemonics unless BTI is enabled.
def : InstAlias<"bti", (HINT 32), 0>;
def : InstAlias<"bti $op", (HINT btihint_op:$op), 0>;
def : InstAlias<"bti r", (HINT 32)>, Requires<[HasBTIE]>;
def : InstAlias<"bti", (HINT 32)>, Requires<[HasBTI]>;
def : InstAlias<"bti $op", (HINT btihint_op:$op)>, Requires<[HasBTI]>;

Expand Down Expand Up @@ -11426,6 +11433,26 @@ let Predicates = [HasCMH] in {
def STCPH : STCPHInst<"stcph">; // Store Concurrent Priority Hint instruction
}

//===----------------------------------------------------------------------===//
// Permission Overlays Extension 2 (FEAT_S1POE2)
//===----------------------------------------------------------------------===//

let Predicates = [HasS1POE2] in {
defm TCHANGEBrr : TCHANGEReg<"tchangeb", true>;
defm TCHANGEFrr : TCHANGEReg<"tchangef", false>;
defm TCHANGEBri : TCHANGEImm<"tchangeb", true>;
defm TCHANGEFri : TCHANGEImm<"tchangef", false>;
}

//===----------------------------------------------------------------------===//
// TIndex Exception-like Vector (FEAT_TEV)
//===----------------------------------------------------------------------===//

let Predicates = [HasTEV] in {
defm TENTER : TENTER<"tenter">;
defm TEXIT : TEXIT<"texit">;
}

include "AArch64InstrAtomics.td"
include "AArch64SVEInstrInfo.td"
include "AArch64SMEInstrInfo.td"
Expand Down
Loading