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[MLIR][XeGPU] Matrix load/store subgroup distribution #165008
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akroviakov
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Nov 3, 2025
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[MLIR][XeGPU] Matrix load/store subgroup distribution
akroviakov f80ee32
Add offset calculation
akroviakov b4f5a4d
Relax `subgroup_block_io` dimensionality restriction
akroviakov 3c4a5aa
Address feedback
akroviakov 5965b54
Remove DistributionLevel enum
akroviakov 246761e
Improve verification
akroviakov c99294a
Improve verification
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Can we add a verification here for load/store_matrix with @subgroup_block_io attribute: The payload must be contiguous in the memory.
Both of these two IRs in the tests added in this PR are actually not correct. Since the payload data are not contiguous between lanes. They are correct if you change the vector<2x16xf32> to <16x2xf32> (lane_layout/lane_data need to change accordingly but that is out of IR verifier's scope).
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Added verification. However,
I understand the logical reasoning for this in the matrix ops case, but the current distribution does not allow it, considering the "correct" lane layout the block load requires.
We have
Meaning that given
lane_layout = [1, 16], lane_data = [1, 1]and a16x2data shape, we getWe can change the layout to be
[16, 1], which would allow the pattern to complete and the distributed code to still be correct, since the lane layout is not used in further coordinate calculations. But[16, 1]may be harder for users to reason about by simply looking at the xevm block load description and the sg-levelsubgroup_block_iomatrix op.There was a problem hiding this comment.
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If user uses stride=[1, 32] in the memory layout, then user should able to reason sg_layout = [16, 1].
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if user use lane_layout = [1, 16], it should not use strided memory layout, the example above should just use block layout. The maxtrix op with subgroup_block_io is a subgroup operation, and all lanes collectively access a contiguous memory buffer.
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There is now a test with a
16x2xf32result using the proper stride.Short snippet:
It distributes to
1x2xf32