[mlir][ROCDL] Add tensor load and store instructions to ROCDL #165016

justinrosner · 2025-10-24T17:25:56Z

Add support for tensor.load.to.lds and tensor.store.from.lds instructions in ROCDL.

github-actions · 2025-10-24T17:26:20Z

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llvmbot · 2025-10-24T17:27:02Z

@llvm/pr-subscribers-mlir-llvm

Author: Justin Rosner (justinrosner)

Changes

Add support for tensor.load.to.lds and tensor.store.from.lds instructions in ROCDL.

Full diff: https://github.com/llvm/llvm-project/pull/165016.diff

3 Files Affected:

(modified) mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td (+44)
(modified) mlir/test/Dialect/LLVMIR/rocdl.mlir (+30)
(modified) mlir/test/Target/LLVMIR/rocdl.mlir (+30)

diff --git a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
index d2df244eb9363..7b240f02653d5 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
@@ -663,6 +663,50 @@ def ROCDL_GlobalLoadLDSOp :
   }];
 }
 
+//===---------------------------------------------------------------------===//
+// Tensor load/store intrinsics (available in GFX1250)
+//===---------------------------------------------------------------------===//
+
+// Base class for tensor load/store operations with 4 descriptor groups
+class ROCDL_TensorLDSIntrOp<string mnemonic> :
+  ROCDL_IntrOp<mnemonic, [], [], [], 0, 0, 1, 0, [4], ["cachePolicy"]> {
+  dag args = (ins LLVM_Type:$dgroup0, LLVM_Type:$dgroup1, LLVM_Type:$dgroup2,
+                  LLVM_Type:$dgroup3, I32Attr:$cachePolicy);
+  let arguments = !con(args, baseArgs);
+  let assemblyFormat = [{
+    $dgroup0 `,` $dgroup1 `,` $dgroup2 `,` $dgroup3 `,` $cachePolicy
+    attr-dict `:` type($dgroup0) `,` type($dgroup1) `,` type($dgroup2) `,` type($dgroup3)
+  }];
+  let extraClassDefinition = [{
+    ::llvm::SmallVector<::mlir::Value> $cppClass::getAccessedOperands() {
+      return {getDgroup0(), getDgroup1(), getDgroup2(), getDgroup3()};
+    }
+  }];
+}
+
+// Base class for tensor load/store operations with 2 descriptor groups
+// (D2 variant)
+class ROCDL_TensorLDSIntrD2Op<string mnemonic> :
+  ROCDL_IntrOp<mnemonic, [], [], [], 0, 0, 1, 0, [2], ["cachePolicy"]> {
+  dag args = (ins LLVM_Type:$dgroup0, LLVM_Type:$dgroup1, I32Attr:$cachePolicy);
+  let arguments = !con(args, baseArgs);
+  let assemblyFormat = [{
+    $dgroup0 `,` $dgroup1 `,` $cachePolicy
+    attr-dict `:` type($dgroup0) `,` type($dgroup1)
+  }];
+  let extraClassDefinition = [{
+    ::llvm::SmallVector<::mlir::Value> $cppClass::getAccessedOperands() {
+      return {getDgroup0(), getDgroup1()};
+    }
+  }];
+}
+
+// Tensor load and store operations
+def ROCDL_TensorLoadToLDSOp : ROCDL_TensorLDSIntrOp<"tensor.load.to.lds">;
+def ROCDL_TensorStoreFromLDSOp : ROCDL_TensorLDSIntrOp<"tensor.store.from.lds">;
+def ROCDL_TensorLoadToLDSD2Op : ROCDL_TensorLDSIntrD2Op<"tensor.load.to.lds.d2">;
+def ROCDL_TensorStoreFromLDSD2Op : ROCDL_TensorLDSIntrD2Op<"tensor.store.from.lds.d2">;
+
 //===---------------------------------------------------------------------===//
 // Operations on raw buffer resources (stride of 0, bounds checks either off or in
 // raw buffer mode).
diff --git a/mlir/test/Dialect/LLVMIR/rocdl.mlir b/mlir/test/Dialect/LLVMIR/rocdl.mlir
index d270ee8b089aa..13c01ddd6b1f2 100644
--- a/mlir/test/Dialect/LLVMIR/rocdl.mlir
+++ b/mlir/test/Dialect/LLVMIR/rocdl.mlir
@@ -664,6 +664,36 @@ llvm.func @rocdl.global.load.lds(%src : !llvm.ptr<1>, %dst: !llvm.ptr<3>) {
   llvm.return
 }
 
+llvm.func @rocdl.tensor.load.to.lds(%dgroup0 : vector<4xi32>, %dgroup1 : vector<8xi32>,
+                                     %dgroup2 : vector<4xi32>, %dgroup3 : vector<4xi32>) {
+  // CHECK-LABEL @rocdl.tensor.load.to.lds
+  // CHECK: rocdl.tensor.load.to.lds %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, 0 : vector<4xi32>, vector<8xi32>, vector<4xi32>, vector<4xi32>
+  rocdl.tensor.load.to.lds %dgroup0, %dgroup1, %dgroup2, %dgroup3, 0 : vector<4xi32>, vector<8xi32>, vector<4xi32>, vector<4xi32>
+  llvm.return
+}
+
+llvm.func @rocdl.tensor.store.from.lds(%dgroup0 : vector<4xi32>, %dgroup1 : vector<8xi32>,
+                                        %dgroup2 : vector<4xi32>, %dgroup3 : vector<4xi32>) {
+  // CHECK-LABEL @rocdl.tensor.store.from.lds
+  // CHECK: rocdl.tensor.store.from.lds %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, 0 : vector<4xi32>, vector<8xi32>, vector<4xi32>, vector<4xi32>
+  rocdl.tensor.store.from.lds %dgroup0, %dgroup1, %dgroup2, %dgroup3, 0 : vector<4xi32>, vector<8xi32>, vector<4xi32>, vector<4xi32>
+  llvm.return
+}
+
+llvm.func @rocdl.tensor.load.to.lds.d2(%dgroup0 : vector<4xi32>, %dgroup1 : vector<8xi32>) {
+  // CHECK-LABEL @rocdl.tensor.load.to.lds.d2
+  // CHECK: rocdl.tensor.load.to.lds.d2 %{{.*}}, %{{.*}}, 0 : vector<4xi32>, vector<8xi32>
+  rocdl.tensor.load.to.lds.d2 %dgroup0, %dgroup1, 0 : vector<4xi32>, vector<8xi32>
+  llvm.return
+}
+
+llvm.func @rocdl.tensor.store.from.lds.d2(%dgroup0 : vector<4xi32>, %dgroup1 : vector<8xi32>) {
+  // CHECK-LABEL @rocdl.tensor.store.from.lds.d2
+  // CHECK: rocdl.tensor.store.from.lds.d2 %{{.*}}, %{{.*}}, 0 : vector<4xi32>, vector<8xi32>
+  rocdl.tensor.store.from.lds.d2 %dgroup0, %dgroup1, 0 : vector<4xi32>, vector<8xi32>
+  llvm.return
+}
+
 llvm.func @rocdl.make.buffer.rsrc(%ptr : !llvm.ptr,
                                   %stride : i16,
                                   %numRecords : i64,
diff --git a/mlir/test/Target/LLVMIR/rocdl.mlir b/mlir/test/Target/LLVMIR/rocdl.mlir
index 30126f6bff05a..ac5e703458ed1 100644
--- a/mlir/test/Target/LLVMIR/rocdl.mlir
+++ b/mlir/test/Target/LLVMIR/rocdl.mlir
@@ -1040,6 +1040,36 @@ llvm.func @rocdl.global.load.lds(%src : !llvm.ptr<1>, %dst: !llvm.ptr<3>) {
   llvm.return
 }
 
+llvm.func @rocdl.tensor.load.to.lds(%dgroup0 : vector<4xi32>, %dgroup1 : vector<8xi32>,
+                                     %dgroup2 : vector<4xi32>, %dgroup3 : vector<4xi32>) {
+  // CHECK-LABEL: rocdl.tensor.load.to.lds
+  // CHECK: call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %{{.*}}, <8 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 0)
+  rocdl.tensor.load.to.lds %dgroup0, %dgroup1, %dgroup2, %dgroup3, 0 : vector<4xi32>, vector<8xi32>, vector<4xi32>, vector<4xi32>
+  llvm.return
+}
+
+llvm.func @rocdl.tensor.store.from.lds(%dgroup0 : vector<4xi32>, %dgroup1 : vector<8xi32>,
+                                        %dgroup2 : vector<4xi32>, %dgroup3 : vector<4xi32>) {
+  // CHECK-LABEL: rocdl.tensor.store.from.lds
+  // CHECK: call void @llvm.amdgcn.tensor.store.from.lds(<4 x i32> %{{.*}}, <8 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 0)
+  rocdl.tensor.store.from.lds %dgroup0, %dgroup1, %dgroup2, %dgroup3, 0 : vector<4xi32>, vector<8xi32>, vector<4xi32>, vector<4xi32>
+  llvm.return
+}
+
+llvm.func @rocdl.tensor.load.to.lds.d2(%dgroup0 : vector<4xi32>, %dgroup1 : vector<8xi32>) {
+  // CHECK-LABEL: rocdl.tensor.load.to.lds.d2
+  // CHECK: call void @llvm.amdgcn.tensor.load.to.lds.d2(<4 x i32> %{{.*}}, <8 x i32> %{{.*}}, i32 0)
+  rocdl.tensor.load.to.lds.d2 %dgroup0, %dgroup1, 0 : vector<4xi32>, vector<8xi32>
+  llvm.return
+}
+
+llvm.func @rocdl.tensor.store.from.lds.d2(%dgroup0 : vector<4xi32>, %dgroup1 : vector<8xi32>) {
+  // CHECK-LABEL: rocdl.tensor.store.from.lds.d2
+  // CHECK: call void @llvm.amdgcn.tensor.store.from.lds.d2(<4 x i32> %{{.*}}, <8 x i32> %{{.*}}, i32 0)
+  rocdl.tensor.store.from.lds.d2 %dgroup0, %dgroup1, 0 : vector<4xi32>, vector<8xi32>
+  llvm.return
+}
+
 llvm.func @rocdl.make.buffer.rsrc(%ptr : !llvm.ptr,
                                   %stride : i16,
                                   %numRecords : i64,

llvmbot · 2025-10-24T17:27:03Z

@llvm/pr-subscribers-mlir

Author: Justin Rosner (justinrosner)

Changes

Add support for tensor.load.to.lds and tensor.store.from.lds instructions in ROCDL.

Full diff: https://github.com/llvm/llvm-project/pull/165016.diff

3 Files Affected:

(modified) mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td (+44)
(modified) mlir/test/Dialect/LLVMIR/rocdl.mlir (+30)
(modified) mlir/test/Target/LLVMIR/rocdl.mlir (+30)

diff --git a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
index d2df244eb9363..7b240f02653d5 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
@@ -663,6 +663,50 @@ def ROCDL_GlobalLoadLDSOp :
   }];
 }
 
+//===---------------------------------------------------------------------===//
+// Tensor load/store intrinsics (available in GFX1250)
+//===---------------------------------------------------------------------===//
+
+// Base class for tensor load/store operations with 4 descriptor groups
+class ROCDL_TensorLDSIntrOp<string mnemonic> :
+  ROCDL_IntrOp<mnemonic, [], [], [], 0, 0, 1, 0, [4], ["cachePolicy"]> {
+  dag args = (ins LLVM_Type:$dgroup0, LLVM_Type:$dgroup1, LLVM_Type:$dgroup2,
+                  LLVM_Type:$dgroup3, I32Attr:$cachePolicy);
+  let arguments = !con(args, baseArgs);
+  let assemblyFormat = [{
+    $dgroup0 `,` $dgroup1 `,` $dgroup2 `,` $dgroup3 `,` $cachePolicy
+    attr-dict `:` type($dgroup0) `,` type($dgroup1) `,` type($dgroup2) `,` type($dgroup3)
+  }];
+  let extraClassDefinition = [{
+    ::llvm::SmallVector<::mlir::Value> $cppClass::getAccessedOperands() {
+      return {getDgroup0(), getDgroup1(), getDgroup2(), getDgroup3()};
+    }
+  }];
+}
+
+// Base class for tensor load/store operations with 2 descriptor groups
+// (D2 variant)
+class ROCDL_TensorLDSIntrD2Op<string mnemonic> :
+  ROCDL_IntrOp<mnemonic, [], [], [], 0, 0, 1, 0, [2], ["cachePolicy"]> {
+  dag args = (ins LLVM_Type:$dgroup0, LLVM_Type:$dgroup1, I32Attr:$cachePolicy);
+  let arguments = !con(args, baseArgs);
+  let assemblyFormat = [{
+    $dgroup0 `,` $dgroup1 `,` $cachePolicy
+    attr-dict `:` type($dgroup0) `,` type($dgroup1)
+  }];
+  let extraClassDefinition = [{
+    ::llvm::SmallVector<::mlir::Value> $cppClass::getAccessedOperands() {
+      return {getDgroup0(), getDgroup1()};
+    }
+  }];
+}
+
+// Tensor load and store operations
+def ROCDL_TensorLoadToLDSOp : ROCDL_TensorLDSIntrOp<"tensor.load.to.lds">;
+def ROCDL_TensorStoreFromLDSOp : ROCDL_TensorLDSIntrOp<"tensor.store.from.lds">;
+def ROCDL_TensorLoadToLDSD2Op : ROCDL_TensorLDSIntrD2Op<"tensor.load.to.lds.d2">;
+def ROCDL_TensorStoreFromLDSD2Op : ROCDL_TensorLDSIntrD2Op<"tensor.store.from.lds.d2">;
+
 //===---------------------------------------------------------------------===//
 // Operations on raw buffer resources (stride of 0, bounds checks either off or in
 // raw buffer mode).
diff --git a/mlir/test/Dialect/LLVMIR/rocdl.mlir b/mlir/test/Dialect/LLVMIR/rocdl.mlir
index d270ee8b089aa..13c01ddd6b1f2 100644
--- a/mlir/test/Dialect/LLVMIR/rocdl.mlir
+++ b/mlir/test/Dialect/LLVMIR/rocdl.mlir
@@ -664,6 +664,36 @@ llvm.func @rocdl.global.load.lds(%src : !llvm.ptr<1>, %dst: !llvm.ptr<3>) {
   llvm.return
 }
 
+llvm.func @rocdl.tensor.load.to.lds(%dgroup0 : vector<4xi32>, %dgroup1 : vector<8xi32>,
+                                     %dgroup2 : vector<4xi32>, %dgroup3 : vector<4xi32>) {
+  // CHECK-LABEL @rocdl.tensor.load.to.lds
+  // CHECK: rocdl.tensor.load.to.lds %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, 0 : vector<4xi32>, vector<8xi32>, vector<4xi32>, vector<4xi32>
+  rocdl.tensor.load.to.lds %dgroup0, %dgroup1, %dgroup2, %dgroup3, 0 : vector<4xi32>, vector<8xi32>, vector<4xi32>, vector<4xi32>
+  llvm.return
+}
+
+llvm.func @rocdl.tensor.store.from.lds(%dgroup0 : vector<4xi32>, %dgroup1 : vector<8xi32>,
+                                        %dgroup2 : vector<4xi32>, %dgroup3 : vector<4xi32>) {
+  // CHECK-LABEL @rocdl.tensor.store.from.lds
+  // CHECK: rocdl.tensor.store.from.lds %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, 0 : vector<4xi32>, vector<8xi32>, vector<4xi32>, vector<4xi32>
+  rocdl.tensor.store.from.lds %dgroup0, %dgroup1, %dgroup2, %dgroup3, 0 : vector<4xi32>, vector<8xi32>, vector<4xi32>, vector<4xi32>
+  llvm.return
+}
+
+llvm.func @rocdl.tensor.load.to.lds.d2(%dgroup0 : vector<4xi32>, %dgroup1 : vector<8xi32>) {
+  // CHECK-LABEL @rocdl.tensor.load.to.lds.d2
+  // CHECK: rocdl.tensor.load.to.lds.d2 %{{.*}}, %{{.*}}, 0 : vector<4xi32>, vector<8xi32>
+  rocdl.tensor.load.to.lds.d2 %dgroup0, %dgroup1, 0 : vector<4xi32>, vector<8xi32>
+  llvm.return
+}
+
+llvm.func @rocdl.tensor.store.from.lds.d2(%dgroup0 : vector<4xi32>, %dgroup1 : vector<8xi32>) {
+  // CHECK-LABEL @rocdl.tensor.store.from.lds.d2
+  // CHECK: rocdl.tensor.store.from.lds.d2 %{{.*}}, %{{.*}}, 0 : vector<4xi32>, vector<8xi32>
+  rocdl.tensor.store.from.lds.d2 %dgroup0, %dgroup1, 0 : vector<4xi32>, vector<8xi32>
+  llvm.return
+}
+
 llvm.func @rocdl.make.buffer.rsrc(%ptr : !llvm.ptr,
                                   %stride : i16,
                                   %numRecords : i64,
diff --git a/mlir/test/Target/LLVMIR/rocdl.mlir b/mlir/test/Target/LLVMIR/rocdl.mlir
index 30126f6bff05a..ac5e703458ed1 100644
--- a/mlir/test/Target/LLVMIR/rocdl.mlir
+++ b/mlir/test/Target/LLVMIR/rocdl.mlir
@@ -1040,6 +1040,36 @@ llvm.func @rocdl.global.load.lds(%src : !llvm.ptr<1>, %dst: !llvm.ptr<3>) {
   llvm.return
 }
 
+llvm.func @rocdl.tensor.load.to.lds(%dgroup0 : vector<4xi32>, %dgroup1 : vector<8xi32>,
+                                     %dgroup2 : vector<4xi32>, %dgroup3 : vector<4xi32>) {
+  // CHECK-LABEL: rocdl.tensor.load.to.lds
+  // CHECK: call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %{{.*}}, <8 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 0)
+  rocdl.tensor.load.to.lds %dgroup0, %dgroup1, %dgroup2, %dgroup3, 0 : vector<4xi32>, vector<8xi32>, vector<4xi32>, vector<4xi32>
+  llvm.return
+}
+
+llvm.func @rocdl.tensor.store.from.lds(%dgroup0 : vector<4xi32>, %dgroup1 : vector<8xi32>,
+                                        %dgroup2 : vector<4xi32>, %dgroup3 : vector<4xi32>) {
+  // CHECK-LABEL: rocdl.tensor.store.from.lds
+  // CHECK: call void @llvm.amdgcn.tensor.store.from.lds(<4 x i32> %{{.*}}, <8 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 0)
+  rocdl.tensor.store.from.lds %dgroup0, %dgroup1, %dgroup2, %dgroup3, 0 : vector<4xi32>, vector<8xi32>, vector<4xi32>, vector<4xi32>
+  llvm.return
+}
+
+llvm.func @rocdl.tensor.load.to.lds.d2(%dgroup0 : vector<4xi32>, %dgroup1 : vector<8xi32>) {
+  // CHECK-LABEL: rocdl.tensor.load.to.lds.d2
+  // CHECK: call void @llvm.amdgcn.tensor.load.to.lds.d2(<4 x i32> %{{.*}}, <8 x i32> %{{.*}}, i32 0)
+  rocdl.tensor.load.to.lds.d2 %dgroup0, %dgroup1, 0 : vector<4xi32>, vector<8xi32>
+  llvm.return
+}
+
+llvm.func @rocdl.tensor.store.from.lds.d2(%dgroup0 : vector<4xi32>, %dgroup1 : vector<8xi32>) {
+  // CHECK-LABEL: rocdl.tensor.store.from.lds.d2
+  // CHECK: call void @llvm.amdgcn.tensor.store.from.lds.d2(<4 x i32> %{{.*}}, <8 x i32> %{{.*}}, i32 0)
+  rocdl.tensor.store.from.lds.d2 %dgroup0, %dgroup1, 0 : vector<4xi32>, vector<8xi32>
+  llvm.return
+}
+
 llvm.func @rocdl.make.buffer.rsrc(%ptr : !llvm.ptr,
                                   %stride : i16,
                                   %numRecords : i64,

mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td

lialan · 2025-10-27T14:29:44Z

mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td

+    attr-dict `:` type($dgroup0) `,` type($dgroup1)
+  }];
+  let extraClassDefinition = [{
+    ::llvm::SmallVector<::mlir::Value> $cppClass::getAccessedOperands() {


same here. see above comments.

mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td

lialan · 2025-10-27T17:10:32Z

mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td

+
+def ROCDL_TensorLoadToLDSIntrOp :
+  ROCDL_IntrOp<"tensor.load.to.lds", [], [], [], 0, 0, 1, 0, [4], ["cachePolicy"]> {
+  dag args = (ins Arg<LLVM_VectorOf<I32>, "", [MemRead]>:$dgroup0,


I am not sure if we want MemRead here, same as MemWrite below.
Here is what I can find:

the source and dest addresses are encoded in d#group 0 (as per manual), group 1,2,3 are other encodings irrelevant of memory addresses.

underlying intrinsic has IntrInaccessibleMemOrArgMemOnly

I think memory properties are best associated with the ROCDL intrinsic instead of the individual arguments. @justinrosner

Do we want to do something like the following instead then?

Add the MemoryEffectOpInterface to each class

Override the getEffects method with something like:

void $cppClass::getEffects( SmallVectorImpl<MemoryEffects::EffectInstance> &effects) { auto inaccessible = mlir::LLVM::InaccessibleMemoryResource::get(); // These intrinsics read and write inaccessible memory (LDS). effects.emplace_back(mlir::MemoryEffects::Read::get(), inaccessible, mlir::Value()); effects.emplace_back(mlir::MemoryEffects::Write::get(), inaccessible, mlir::Value()); }

Does this give a better matching with what the underlying LLVM intrinsic is doing?

I quickly looked around, it seems the best we can do is to use RecursiveMemoryEffects to represent this op.

So it could be like:

ROCDL_IntrOp<"tensor.load.to.lds", [], [], [RecursiveMemoryEffects]...

Let me know what you think.

I thought that RecursiveMemoryEffects was meant for ops that contain regions and want their memory behavior to be the union of the effects of the nested ops? The new ops have a 1:1 mapping with the intrinsics, so they are not going to have any regions. So wouldn't marking them as recursive have no effect here?

I believe here is a design question: per the manual, TENSOR_LOAD_TO_LDS will be decomposed into a series of GLOBAL_LOAD_ASYNC_TO_LDS internally as it is using TDM. So it is intrinsically doing something more.

But looking around, I don't see other ROCDL ops that works on mem actually have related memory traits. So I guess it is okay to skip it.

lialan

LGTM.

justinrosner · 2025-10-27T19:50:45Z

@lialan I don't have permission to run the required CI tests/merge. Are you able to help out with this?

kuhar · 2025-10-27T19:51:45Z

@lialan I don't have permission to run the required CI tests/merge. Are you able to help out with this?

Please wait for a review from @krzysz00 before merging

mlir/test/Target/LLVMIR/rocdl.mlir

mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td

mlir/test/Dialect/LLVMIR/rocdl.mlir

mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td

kuhar · 2025-10-28T19:52:55Z

@krzysz00 is busy at llvm dev, I'm going to merge and we can fix forward if he comes back with some more comments

kuhar · 2025-10-28T19:55:13Z

@justinrosner can you make your github email public before we merge? See https://discourse.llvm.org/t/hidden-emails-on-github-should-we-do-something-about-it/74223

justinrosner · 2025-10-28T19:57:57Z

@justinrosner can you make your github email public before we merge? See https://discourse.llvm.org/t/hidden-emails-on-github-should-we-do-something-about-it/74223

I just went in and updated this. Let me know if you need anything else from me!

github-actions · 2025-10-28T20:05:51Z

@justinrosner Congratulations on having your first Pull Request (PR) merged into the LLVM Project!

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…65016) Add support for `tensor.load.to.lds` and `tensor.store.from.lds` instructions in ROCDL.

[mlir][ROCDL] Add tensor load and store instructions to ROCDL

1bea035

justinrosner requested review from krzysz00 and kuhar as code owners October 24, 2025 17:25

llvmbot added mlir:llvm mlir labels Oct 24, 2025

Merge branch 'main' into justinr-rocdl-tensor-load-store

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kuhar requested a review from lialan October 27, 2025 12:29

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Update Arg types

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justinrosner requested a review from lialan October 27, 2025 16:08

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Remove mem properties

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kuhar reviewed Oct 27, 2025

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Update LIT tests and add description to ops

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justinrosner requested a review from kuhar October 28, 2025 13:39

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[ROCDL] Added tensor load/store ops #165390

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ravil-mobile reviewed Oct 28, 2025

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Attend to more review comments

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justinrosner requested a review from ravil-mobile October 28, 2025 16:03

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Add back unique types to assembly string

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justinrosner requested a review from kuhar October 28, 2025 17:14

kuhar enabled auto-merge (squash) October 28, 2025 19:53

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kuhar enabled auto-merge (squash) October 28, 2025 20:01

kuhar merged commit 303fba0 into llvm:main Oct 28, 2025
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aokblast pushed a commit to aokblast/llvm-project that referenced this pull request Oct 30, 2025

[mlir][ROCDL] Add tensor load and store instructions to ROCDL (llvm#1…

848de47

…65016) Add support for `tensor.load.to.lds` and `tensor.store.from.lds` instructions in ROCDL.

DEBADRIBASAK pushed a commit to DEBADRIBASAK/llvm-project that referenced this pull request Nov 3, 2025

[mlir][ROCDL] Add tensor load and store instructions to ROCDL (llvm#1…

d3f894b

…65016) Add support for `tensor.load.to.lds` and `tensor.store.from.lds` instructions in ROCDL.

[mlir][ROCDL] Add tensor load and store instructions to ROCDL #165016

[mlir][ROCDL] Add tensor load and store instructions to ROCDL #165016

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