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[AMDGPU] Add pattern to select scalar ops for fshr with uniform operands #165295

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[AMDGPU] Add pattern to select scalar ops for fshr with uniform operands #165295

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f03b6f9
add ISEL pattern for fshr with uniform operands
akadutta Oct 27, 2025
adf0f19
remove redundant S_ADD nop
akadutta Oct 28, 2025
a46e108
replace previous instr sequence with reg_sequence and s_lshr_b64 base…
akadutta Oct 29, 2025
a862618
extending new uniform patterns to all fshr cases;tests updated
akadutta Nov 1, 2025
418c8fb
limit pattern to gfx9+; reduce multiple occurences of same pattern
akadutta Nov 4, 2025
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5 changes: 5 additions & 0 deletions llvm/lib/Target/AMDGPU/SIInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -2763,6 +2763,11 @@ def : GCNPat<(fshr i32:$src0, i32:$src1, i32:$src2),
/* src2_modifiers */ 0,
$src2, /* clamp */ 0, /* op_sel */ 0)
>;

def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
(S_OR_B32 (S_LSHR_B32 $src1, (S_AND_B32 $src2, (i32 0xffffffff))), (S_LSHL_B32 $src0, (S_SUB_I32 (i32 32), (S_AND_B32 $src2, (i32 0xffffffff)))))
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@jayfoad jayfoad Oct 28, 2025

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A 32-bit AND with 0xffffffff is a no-op. Do not generate this.

>;

} // end True16Predicate = UseFakeTrue16Insts

/********** ====================== **********/
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