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Merged
merged 4 commits into from
Oct 31, 2025
Merged

Extend NVVM mma ops to support fp64 #165380

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f03a9cb
Extend gpu and nvvm wmma to support fp64
castigli Oct 28, 2025
5b4b363
Keep only nvvm changes
castigli Oct 29, 2025
bd21220
format
castigli Oct 29, 2025
2cac7bf
address review, add invalid test for load frag a f64
castigli Oct 31, 2025
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16 changes: 14 additions & 2 deletions mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
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Original file line number Diff line number Diff line change
Expand Up @@ -2014,6 +2014,9 @@ class MMA_LDST_OPS<list<GEOM> Geom, list<string> Frags, list<string> Types> {
// llvm supports and can be extended as needed.
class NVVM_MMA_OPS {
// "wmma" operations
list<list<WMMA_REGS>> fp64_wmma_ops = MMA_OPS<
[GEOM<8, 8, 4>],
["f64"], [], ["f64"], []>.ret;
list<list<WMMA_REGS>> tf32_wmma_ops = MMA_OPS<
[GEOM<16, 16, 8>],
["tf32"], [], ["f32"], []>.ret;
Expand All @@ -2024,6 +2027,7 @@ class NVVM_MMA_OPS {
[GEOM<16, 16, 16>, GEOM<32, 8, 16>, GEOM<8, 32, 16>],
["s8","u8"], [], ["s32"], []>.ret;
list<list<WMMA_REGS>> all_wmma_ops = !listconcat(
fp64_wmma_ops,
tf32_wmma_ops,
fp_wmma_ops,
i8_wmma_ops);
Expand All @@ -2040,9 +2044,17 @@ class NVVM_MMA_OPS {
list<WMMA_REGS> ldst_tf32_cd_ops = MMA_LDST_OPS<
[GEOM<16, 16, 8>],
["c", "d"], ["f32"]>.ret;
list<WMMA_REGS> ldst_f64_ab_ops = MMA_LDST_OPS<
[GEOM<8, 8, 4>],
["a", "b"], ["f64"]>.ret;
list<WMMA_REGS> ldst_f64_cd_ops = MMA_LDST_OPS<
[GEOM<8, 8, 4>],
["c", "d"], ["f64"]>.ret;
list<WMMA_REGS> all_ldst_ops = !listconcat(ldst_ab_ops, ldst_cd_ops,
ldst_tf32_ab_ops,
ldst_tf32_cd_ops);
ldst_tf32_cd_ops,
ldst_f64_ab_ops,
ldst_f64_cd_ops);
// Separate A/B/C fragments (loads) from D (stores).
list<WMMA_REGS> all_ld_ops = !filter(op, all_ldst_ops, !ne(op.frag, "d"));
list<WMMA_REGS> all_st_ops = !filter(op, all_ldst_ops, !eq(op.frag, "d"));
Expand Down Expand Up @@ -2349,7 +2361,7 @@ def MMAFragAttr : EnumAttr<NVVM_Dialect, MMAFrag, "mma_frag"> {
}

def NVVM_WMMALoadOp: NVVM_Op<"wmma.load">,
Results<(outs LLVM_AnyStruct:$res)>,
Results<(outs AnyTypeOf<[LLVM_AnyStruct, F64]>:$res)>,
Arguments<(ins LLVM_AnyPointer: $ptr, I32: $stride, I32Attr:$m,
I32Attr:$n, I32Attr:$k, MMALayoutAttr:$layout,
MMATypesAttr:$eltype, MMAFragAttr:$frag)> {
Expand Down
14 changes: 14 additions & 0 deletions mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
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Expand Up @@ -896,6 +896,12 @@ std::pair<mlir::Type, unsigned> NVVM::inferMMAType(NVVM::MMATypes type,
} else if (type == NVVM::MMATypes::f32) {
elementType = builder.getF32Type();
numberElements = 8;
} else if (type == NVVM::MMATypes::f64) {
elementType = builder.getF64Type();
if (frag == NVVM::MMAFrag::a || frag == NVVM::MMAFrag::b)
numberElements = 1;
else
numberElements = 2;
} else if (type == NVVM::MMATypes::tf32) {
elementType = builder.getI32Type();
numberElements = 4;
Expand Down Expand Up @@ -954,6 +960,14 @@ LogicalResult NVVM::WMMALoadOp::verify() {
return emitOpError() << "invalid attribute combination";
std::pair<Type, unsigned> typeInfo = inferMMATypeFromMNK(
getEltype(), getFrag(), getM(), getN(), getK(), getContext());
// Special case for f64 fragments
Type f64Ty = Float64Type::get(getContext());
if (typeInfo.first == f64Ty && typeInfo.second == 1) {
if (getType() != f64Ty)
return emitOpError("expected destination type to be f64");
return success();
}
// Everything else is a struct
Type dstType = LLVM::LLVMStructType::getLiteral(
getContext(), SmallVector<Type, 8>(typeInfo.second, typeInfo.first));
if (getType() != dstType)
Expand Down
37 changes: 37 additions & 0 deletions mlir/test/Target/LLVMIR/nvvmir.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -463,6 +463,43 @@ llvm.func @nvvm_wmma_mma(%0 : i32, %1 : i32, %2 : i32, %3 : i32, %4 : i32, %5 :
llvm.return
}

// CHECK-LABEL: @nvvm_wmma_load_a_f64
llvm.func @nvvm_wmma_load_a_f64(%arg0: !llvm.ptr, %arg1 : i32) {
// CHECK: call double @llvm.nvvm.wmma.m8n8k4.load.a.row.stride.f64.p0(ptr %{{.*}}, i32 %{{.*}})
%0 = nvvm.wmma.load %arg0, %arg1
{eltype = #nvvm.mma_type<f64>, frag = #nvvm.mma_frag<a>, k = 4 : i32, layout = #nvvm.mma_layout<row>, m = 8 : i32, n = 8 : i32}
: (!llvm.ptr) -> f64
llvm.return
}

// CHECK-LABEL: @nvvm_wmma_load_c_f64
llvm.func @nvvm_wmma_load_c_f64(%arg0: !llvm.ptr, %arg1 : i32) {
// CHECK: call { double, double } @llvm.nvvm.wmma.m8n8k4.load.c.row.stride.f64.p0(ptr %{{.*}}, i32 %{{.*}})
%0 = nvvm.wmma.load %arg0, %arg1
{eltype = #nvvm.mma_type<f64>, frag = #nvvm.mma_frag<c>, k = 4 : i32, layout = #nvvm.mma_layout<row>, m = 8 : i32, n = 8 : i32}
: (!llvm.ptr) -> !llvm.struct<(f64, f64)>
llvm.return
}

// CHECK-LABEL: @nvvm_wmma_mma_f64
llvm.func @nvvm_wmma_mma_f64(%0 : f64, %1 : f64, %2 : f64, %3 : f64) {
// CHECK: { double, double } @llvm.nvvm.wmma.m8n8k4.mma.row.col.f64(double %{{.*}}, double %{{.*}}, double %{{.*}}, double %{{.*}})
%r = nvvm.wmma.mma %0, %1, %2, %3
{eltypeA = #nvvm.mma_type<f64>, eltypeB = #nvvm.mma_type<f64>, k = 4 : i32, layoutA = #nvvm.mma_layout<row>, layoutB = #nvvm.mma_layout<col>, m = 8 : i32, n = 8 : i32}
: (f64, f64, f64, f64)
-> !llvm.struct<(f64, f64)>
llvm.return
}

// CHECK-LABEL: @nvvm_wmma_store_d_f64
llvm.func @nvvm_wmma_store_d_f64(%arg0: !llvm.ptr, %arg1 : i32, %arg2 : f64, %arg3 : f64) {
// CHECK: call void @llvm.nvvm.wmma.m8n8k4.store.d.row.stride.f64.p0(ptr %{{.*}}, double %{{.*}}, double %{{.*}}, i32 %{{.*}})
nvvm.wmma.store %arg0, %arg1, %arg2, %arg3
{eltype = #nvvm.mma_type<f64>, k = 4 : i32, layout = #nvvm.mma_layout<row>, m = 8 : i32, n = 8 : i32}
: !llvm.ptr, f64, f64
llvm.return
}

// CHECK-LABEL: @cp_async
llvm.func @cp_async(%arg0: !llvm.ptr<3>, %arg1: !llvm.ptr<1>) {
// CHECK: call void @llvm.nvvm.cp.async.ca.shared.global.4(ptr addrspace(3) %{{.*}}, ptr addrspace(1) %{{.*}})
Expand Down